Semiconductor device, method for manufacturing the same, and electronic device having the same

ABSTRACT

In a thin film transistor including an oxide semiconductor, an oxide cluster having higher electrical conductance than the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer, whereby field effect mobility of the thin film transistor can be increased and increase of off current can be suppressed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device including an oxide semiconductor, a display device including the semiconductor device, and a manufacturing method thereof.

2. Description of the Related Art

Various metal oxides are used for a variety of applications. Indium oxide is a well-known material and is used as a light-transmitting electrode material which is necessary for liquid crystal displays and the like.

Some metal oxides have semiconductor characteristics. Metal oxides having semiconductor characteristics are a kind of compound semiconductor. The compound semiconductor is a semiconductor formed using two or more kinds of atoms bonded together. In general, metal oxides become insulators. However, it is known that metal oxides become semiconductors depending on the combination of elements included in the metal oxides.

For example, it is known that tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like are metal oxides which have semiconductor characteristics. A thin film transistor in which a transparent semiconductor layer which is formed using such a metal oxide serves as a channel formation region is disclosed (Patent Documents 1 to 4 and Non-Patent Document 1).

Further, not only simple (unitary) oxides but also multiple oxides are known as metal oxides. For example, InGaO₃(ZnO)_(m) (m is a natural number) which is a homologous compound is a known material (Non-Patent Documents 2 to 4).

Furthermore, it is confirmed that such an In—Ga—Zn-based oxide is applicable to a channel layer of a thin film transistor (also referred to as a “TFT”) (Patent Document 5 and Non-Patent Documents 5 and 6).

In a conventional technique, amorphous silicon or polycrystalline silicon has been used for a thin film transistor (a TFT) provided for each pixel of an active matrix liquid crystal display. However, in place of these silicon materials, attention has been attracted to a technique for manufacturing a thin film transistor including the aforementioned metal oxide semiconductor. Examples of the techniques are disclosed in Patent Document 6 and Patent Document 7, where a thin film transistor is manufactured with zinc oxide or an In—Ga—Zn—O-based oxide semiconductor for a metal oxide semiconductor film and is used as a switching element or the like of an image display device.

REFERENCE Patent Documents

-   [Patent Document 1] Japanese Published Patent Application No.     S60-198861 -   [Patent Document 2] Japanese Published Patent Application No.     H8-264794 -   [Patent Document 3] Japanese Translation of PCT International     Application No. H11-505377 -   [Patent Document 4] Japanese Published Patent Application No.     2000-150900 -   [Patent Document 5] Japanese Published Patent Application No.     2004-103957 -   [Patent Document 6] Japanese Published Patent Application No.     2007-123861 -   [Patent Document 7] Japanese Published Patent Application No.     2007-96055

[Non-Patent Document]

-   [Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G.     Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M.     Wolf, “A ferroelectric transparent thin-film transistor”, Appl.     Phys. Lett., 17 Jun. 1996, Vol. 68, pp. 3650-3652 -   [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, “The     Phase Relations in the In₂O₃—Ga₂ZnO₄—ZnO System at 1350° C.”, J.     Solid State Chem., 1991, Vol. 93, pp. 298-315 -   [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura,     “Syntheses and Single-Crystal Data of Homologous Compounds,     In₂O₃(ZnO)_(m) (m=3, 4, and 5), InGaO₃(ZnO)₃, and Ga₂O₃(ZnO)_(m),     (m=7, 8, 9, and 16) in the In₂O₃—ZnGa₂O₄—ZnO System”, J. Solid State     Chem., 1995, Vol. 116, pp. 170-178 -   [Non-Patent Document 4] M. Nakamura, N. Kimizuka, T. Mohri, and M.     Isobe, “Syntheses and crystal structures of new homologous     compounds, indium iron zinc oxides (InFeO₃(ZnO)_(m)) (m: natural     number) and related compounds”, KOTAI BUTSURI (SOLID STATE PHYSICS),     1993, Vol. 28, No. 5, pp. 317-327 -   [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M.     Hirano, and H. Hosono, “Thin-film transistor fabricated in     single-crystalline transparent oxide semiconductor”, SCIENCE, 2003,     Vol. 300, pp. 1269-1272 -   [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M.     Hirano, and H. Hosono, “Room-temperature fabrication of transparent     flexible thin-film transistors using amorphous oxide     semiconductors”, NATURE, 2004, Vol. 432, pp. 488-492

SUMMARY OF THE INVENTION

The field effect mobility of a thin film transistor where a channel formation region is provided in an oxide semiconductor layer is approximately 10 times to 100 times as high as that of a thin film transistor including amorphous silicon. The oxide semiconductor film can be formed by a sputtering method or the like at a temperature of 300° C. or lower; thus, the manufacturing process thereof is easier than that of a thin film transistor including polycrystalline silicon. Thus, a pixel portion and a peripheral driver circuit of a display device can be formed over one substrate even in the case where a large-sized substrate is used.

In an active matrix liquid crystal display device, a large amount of drive current needs to flow because application of voltage to a liquid crystal layer and charge of a storage capacitor are performed during a short gate-switching period. In particular, in a liquid crystal display device with a large screen or a high-definition liquid crystal display device, a larger amount of drive current is necessary. Therefore, it is preferable that a thin film transistor used as a switching element have high field effect mobility.

However, the field effect mobility of a thin film transistor including an oxide semiconductor is lower than that of a thin film transistor including polycrystalline silicon, which has been used for a driver circuit of a conventional liquid crystal display device.

Thus, an object according to an embodiment of the present invention is to improve field effect mobility of a thin film transistor including an oxide semiconductor. Another object according to an embodiment of the present invention is to suppress increase of off current even when the field effect mobility of the thin film transistor is increased. Further, another object according to an embodiment of the present invention is to provide a display device having thin film transistors including the oxide semiconductor.

According to an embodiment of the present invention, it is summarized that in forming a thin film transistor, an oxide semiconductor layer is used and an oxide cluster having higher electrical conductance than the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer.

According to one embodiment of the present invention, a semiconductor device includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a plurality of oxide clusters over the gate insulating layer, an oxide semiconductor layer over the gate insulating layer and the plurality of oxide clusters, and source and drain electrode layers over the oxide semiconductor layer, in which the plurality of oxide clusters have electrical conductivity, the oxide semiconductor layer and the source electrode layer are electrically connected to each other, and the oxide semiconductor layer and the drain electrode layer are electrically connected to each other.

According to another embodiment of the present invention, a semiconductor device includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a plurality of oxide clusters over the gate insulating layer, an oxide semiconductor layer over the gate insulating layer and the plurality of oxide clusters, a buffer layer having n-type electrical conductivity over the oxide semiconductor layer, and source and drain electrode layers over the buffer layer, in which the plurality of oxide clusters have electrical conductivity, a carrier concentration of the buffer layer is higher than a carrier concentration of the oxide semiconductor layer, the oxide semiconductor layer and the source electrode layer are electrically connected to each other with the buffer layer interposed therebetween, and the oxide semiconductor layer and the drain electrode layer are electrically connected to each other with the buffer layer interposed therebetween.

Note that the plurality of oxide clusters preferably include any of indium, zinc, tin, molybdenum, or tungsten. In addition, the plurality of oxide clusters preferably include any of indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, molybdenum oxide, or tungsten oxide. Moreover, electrical conductance of the plurality of oxide clusters is preferably higher than electrical conductance of the oxide semiconductor layer. Further, a height of the plurality of oxide clusters from a reference surface in contact with the gate insulating layer is preferably equal to or greater than 3 nm and equal to or less than 5 nm.

Note that the oxide semiconductor layer and the buffer layer preferably include any of indium, gallium, or zinc. In addition, a film thickness of the oxide semiconductor layer is preferably equal to or greater than 30 nm and equal to or less than 100 nm.

Note that the oxide semiconductor layer preferably has a region which is between the source and drain electrode layers and whose thickness is smaller than the thickness of a region overlapping with the source and drain electrode layers. In addition, a channel protective layer including an inorganic material may be formed over the oxide semiconductor layer.

According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes the steps of forming a gate electrode layer over a substrate, forming a gate insulating layer over the gate electrode layer, forming a plurality of oxide clusters having electrical conductivity over the gate insulating layer in a dispersed manner, forming an oxide semiconductor film over the gate insulating layer and the plurality of oxide clusters by a sputtering method, forming an island-like second oxide semiconductor film by etching the oxide semiconductor film, forming a conductive layer over the island-like second oxide semiconductor film, and forming an oxide semiconductor layer and source and drain electrode layers by etching the island-like second oxide semiconductor film and the conductive layer. Note that electrical conductance of the plurality of oxide clusters is preferably made higher than electrical conductance of the oxide semiconductor layer.

Note that in this specification, a “cluster” refers to a structural unit including a plurality of atoms or molecules, which does not have a film structure, and an “oxide cluster” refers to a cluster which includes oxide having electrical conductivity.

Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps and the stacking order of layers. In addition, the ordinal numbers in this specification do not denote particular names which specify the invention.

Note that the semiconductor devices in this specification indicate all the devices which can operate using semiconductor characteristics, and an electronic optical device, a semiconductor circuit, and an electronic device are all included in the semiconductor devices.

According to an embodiment of the present invention, in a thin film transistor including an oxide semiconductor, field effect mobility of the thin film transistor can be increased by formation of an oxide cluster having higher electrical conductance than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer. In addition, increase of off current can be suppressed even when the field effect mobility of the thin film transistor is increased.

According to an embodiment of the present invention, a display device with high electric characteristics and high reliability can be provided using the thin film transistor in a pixel portion or a driver circuit portion of the display device.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1C illustrate a semiconductor device according to an embodiment of the present invention;

FIGS. 2A to 2C illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 3A to 3C illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 4 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 5 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 6 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 7 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 8A1 and 8A2 and FIGS. 8B1 and 8B2 illustrate a semiconductor device according to an embodiment of the present invention;

FIG. 9 illustrates a semiconductor device according to an embodiment of the present invention;

FIG. 10 illustrates a semiconductor device according to an embodiment of the present invention;

FIGS. 11A to 11C illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 12 illustrates a semiconductor device according to an embodiment of the present invention;

FIG. 13 illustrates a semiconductor device according to an embodiment of the present invention;

FIGS. 14A and 14B are each a block diagram illustrating a semiconductor device;

FIG. 15 illustrates a configuration of a signal-line driver circuit;

FIG. 16 is a timing chart illustrating operation of a signal-line driver circuit;

FIG. 17 is a timing chart illustrating operation of a signal-line driver circuit;

FIG. 18 illustrates a configuration of a shift register;

FIG. 19 illustrates a connection configuration of the flip-flop illustrated in FIG. 18;

FIG. 20 illustrates a pixel equivalent circuit of a semiconductor device according to an embodiment of the present invention;

FIGS. 21A to 21C illustrate a semiconductor device according to an embodiment of the present invention;

FIGS. 22A1 and 22A2 and FIG. 22B illustrate a semiconductor device according to an embodiment of the present invention;

FIG. 23 illustrates a semiconductor device according to an embodiment of the present invention;

FIGS. 24A and 24B illustrate a semiconductor device according to an embodiment of the present invention;

FIGS. 25A and 25B each illustrate an example of a usage pattern of electronic paper;

FIG. 26 is an external view of an example of an electronic book;

FIG. 27A is an external view of an example of a television device and FIG. 27B is an external view of an example of a digital photo frame;

FIGS. 28A and 28B each illustrate an example of an amusement machine;

FIGS. 29A and 29B each illustrate an example of a cellular phone;

FIGS. 30A to 30C illustrate a semiconductor device according to an embodiment of the present invention; and

FIGS. 31A and 31B illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments according to one embodiment of the present invention are described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the modes and details disclosed herein can be modified in a variety of ways without departing from the scope and the spirit of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments given below. Note that in the structure of the present invention described below, the same portion or a portion having a similar function is denoted by the same reference numeral in all drawings, and the description thereof is omitted.

Embodiment 1

In this embodiment, a structure of a thin film transistor will be described with reference to FIGS. 1A to 1C.

A thin film transistor having a bottom-gate structure of this embodiment is illustrated in FIGS. 1A to 1C. FIG. 1A is a cross-sectional view, and FIG. 1B is a plan view. FIG. 1A is a cross-sectional view taken along line A1-A2 of FIG. 1B. In addition, FIG. 1C is an enlarged view of an oxide semiconductor layer 103 of FIG. 1A.

In the thin film transistor illustrated in FIGS. 1A to 1C, a gate electrode layer 101 is provided over a substrate 100, a gate insulating layer 102 is provided over the gate electrode layer 101, a plurality of oxide clusters 106 are provided over the gate insulating layer 102 in a dispersed manner, the oxide semiconductor layer 103 is provided over the gate insulating layer 102 and the oxide clusters 106, and source and drain electrode layers 105 a and 105 b are provided over the oxide semiconductor layer 103. Here, the oxide semiconductor layer 103 and the source electrode layer 105 a are electrically connected to each other, and the oxide semiconductor layer 103 and the drain electrode layer 105 b are electrically connected to each other. Note that at least part of the oxide semiconductor layer 103 is provided in contact with an upper surface of the gate insulating layer 102.

The gate electrode layer 101 can be formed to have a single-layer structure or a stacked structure using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium; an alloy material containing any of these metal materials as its main component; or a nitride containing any of these metal materials as its component. The gate electrode layer 101 is preferably formed using a low-resistance conductive material such as aluminum or copper; however, the low-resistance conductive material has disadvantages of low heat resistance and being easily eroded. Thus, the low-resistance conductive material is preferably used in combination with a heat-resistant conductive material. As the heat-resistant conductive material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like is used.

For example, as a stacked structure of the gate electrode layer 101, a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked is preferable. Alternatively, a three-layer structure in which a tungsten layer or a tungsten nitride layer, a layer using an aluminum-silicon alloy layer or an aluminum-titanium alloy layer, and a titanium nitride layer or a titanium layer are stacked is preferably used.

As an oxide semiconductor which forms the oxide semiconductor layer 103, it is preferable to use an oxide semiconductor whose composition formula is represented by InMO₃(ZnO)_(m) (m>0). In particular, it is preferable to use an In—Ga—Zn—O-based oxide semiconductor. Note that M denotes one or more of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in addition to a case where only Ga is contained as M, there is a case where Ga and the above metal elements other than Ga, for example, Ga and Ni or Ga and Fe are contained as M. Moreover, in the oxide semiconductor, in some cases, a transition metal element such as Fe or Ni or an oxide of the transition metal is contained as an impurity element in addition to a metal element contained as M. In this specification, among the oxide semiconductors whose composition formulas are represented by InMO₃(ZnO)_(m) (m>0), an oxide semiconductor whose composition formula includes at least Ga as M is referred to as an In—Ga—Zn—O-based oxide semiconductor, and a thin film of the In—Ga—Zn—O-based oxide semiconductor is referred to as an In—Ga—Zn—O-based non-single-crystal film.

An amorphous structure is observed in the In—Ga—Zn—O-based non-single-crystal film by X-ray diffraction (XRD). Note that heat treatment is performed on the In—Ga—Zn—O-based non-single-crystal film of the examined sample at 200° C. to 700° C., typically 250° C. to 500° C., for 10 minutes to 100 minutes after the film is formed by a sputtering method.

In addition, the In—Ga—Zn—O-based non-single-crystal film is used as an active layer of a thin film transistor, whereby a thin film transistor having electric characteristics such as an on/off ratio of 10⁹ or more and a mobility of 10 cm²/Vs or more at a gate voltage of ±20 V can be manufactured.

However, the oxide semiconductor which forms the oxide semiconductor layer 103 is not limited to the oxide semiconductor whose composition formula is represented by InMO₃(ZnO)_(m) (m>0). For example, an oxide semiconductor layer including an indium oxide (InO_(x)), zinc oxide (ZnO_(x)), tin oxide (SnO_(x)), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), gallium-doped zinc oxide (GZO), or the like may be used.

The thickness of the oxide semiconductor layer 103 is set to be 10 nm or more, preferably 30 nm to 100 nm The oxide semiconductor layer 103 has a region which is between the source and drain electrode layers 105 a and 105 b and whose thickness is smaller than the thickness of a region overlapping with the source and drain electrode layers 105 a and 105 b.

The range of the carrier concentration of the oxide semiconductor layer 103 is preferably lower than 1×10¹⁷/cm³ (more preferably, 1×10¹¹/cm³ or higher). When the carrier concentration of the oxide semiconductor layer 103 exceeds the above range, the thin film transistor has a risk of being normally on.

An insulating impurity may be contained in the oxide semiconductor layer 103. As the impurity, insulating oxide typified by silicon oxide, germanium oxide, aluminum oxide, or the like; insulating nitride typified by silicon nitride, aluminum nitride, or the like; or insulating oxynitride such as silicon oxynitride or aluminum oxynitride is applied.

The insulating oxide or the insulating nitride is added to the oxide semiconductor at a concentration at which electrical conductivity of the oxide semiconductor does not deteriorate.

Insulating impurity is contained in the oxide semiconductor layer 103, whereby crystallization of the oxide semiconductor layer 103 can be suppressed. The crystallization of the oxide semiconductor layer 103 is suppressed, whereby characteristics of the thin film transistor can be stabilized.

In addition, the In—Ga—Zn—O-based oxide semiconductor is made to contain the impurity such as silicon oxide. Thus, crystallization of the oxide semiconductor or generation of microcrystal grains can be prevented even by heat treatment at 300° C. to 600° C.

In a manufacturing process of the thin film transistor in which an In—Ga—Zn—O-based oxide semiconductor is a channel formation region, an S value (a subthreshold swing value) or field effect mobility can be improved by performing heat treatment. Moreover, the In—Ga—Zn—O-based oxide semiconductor is made to contain the impurity such silicon oxide, whereby the thin film transistor can be prevented from being normally-on. Further, even in the case where heat stress or bias stress is added to the thin film transistor, variations in a threshold voltage can be prevented.

As the oxide semiconductor applied to the oxide semiconductor layer 103, any of the following oxide semiconductors can be applied in addition to the above: an In—Sn—Zn—O-based oxide semiconductor; an In—Al—Zn—O-based oxide semiconductor; a Sn—Ga—Zn—O-based oxide semiconductor; an Al—Ga—Zn—O-based oxide semiconductor; a Sn—Al—Zn—O-based oxide semiconductor; an In—Zn—O-based oxide semiconductor; a Sn—Zn—O-based oxide semiconductor; an Al—Zn—O-based oxide semiconductor; an In—O-based oxide semiconductor; a Sn—O-based oxide semiconductor; and a Zn—O-based oxide semiconductor. In other words, an impurity which suppresses crystallization to keep an amorphous state is added to these oxide semiconductors, whereby characteristics of the thin film transistor can be stabilized.

The oxide cluster 106 is a cluster having higher electrical conductance than the oxide semiconductor layer 103 which includes oxide having electrical conductivity. In addition, as the oxide, any of indium (In), zinc (Zn), tin (Sn), molybdenum (Mo), or tungsten (W) is preferably included. In particular, indium oxide (InO_(x)), zinc oxide (ZnO_(x)), indium tin oxide (ITO), indium zinc oxide (IZO), molybdenum oxide, or tungsten oxide is preferably used. However, a compound different from the oxide semiconductor layer 103 is preferably used for the oxide cluster 106. Note that the oxide cluster 106 may be crystallized.

In addition, a height R of the oxide cluster 106 is greater than 0 nm and equal to or less than 10 nm, preferably 3 nm to 5 nm inclusive. Here, the height R of the oxide cluster 106 is preferably equal to or less than half of the film thickness of the oxide semiconductor layer 103. As illustrated in FIG. 1C, the height R here is the height of the oxide cluster 106 from a reference surface in which a plane of the gate insulating layer 102 and the oxide cluster 106 are in contact with each other. In addition, the shape of the oxide cluster 106 is not limited to a semispherical shape like the oxide cluster 106 a of FIG. 1C. For example, the oxide cluster 106 may have a semispherical shape which is flattened horizontally like an oxide cluster 106 b or may have a semispherical shape which is flattened vertically like an oxide cluster 106 c. In addition, although the oxide cluster 106 schematically has a semispherical shape, the shape of the oxide cluster 106 is not limited thereto. For example, the oxide cluster 106 may have a sharp needle shape.

In a channel formation region of the oxide semiconductor layer 103, the plurality of oxide clusters 106 are provided in a dispersed manner. Drain current flows through the oxide cluster 106 having high electrical conductance when the thin film transistor is turned on, whereby the field effect mobility can be increased. Further, the oxide semiconductor layer 103 prevents carrier excitation when the thin film transistor is turned off, whereby increase in off current can be suppressed.

The source or drain electrode layer 105 a has a three-layer structure of a first conductive layer 112 a, a second conductive layer 113 a, and a third conductive layer 114 a while the source or drain electrode layer 105 b has a three-layer structure of a first conductive layer 112 b, a second conductive layer 113 b, and a third conductive layer 114 b. Each of the first conductive layers 112 a and 112 b, the second conductive layers 113 a and 113 b, and the third conductive layers 114 a and 114 b can be formed using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium; an alloy material containing any of these metal materials as its main component; or a nitride containing any of these metal materials as its component. Each of the first conductive layers 112 a and 112 b, the second conductive layers 113 a and 113 b, and the third conductive layers 114 a and 114 b is preferably formed using a low-resistance conductive material such as aluminum or copper; however, the low-resistance conductive material has disadvantages of low heat resistance and being easily eroded. Thus, the low-resistance conductive material is preferably used in combination with a heat-resistant conductive material. As the heat-resistant conductive material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like is used.

For example, it is preferable that the first conductive layers 112 a and 112 b and the third conductive layers 114 a and 114 b be formed using titanium that is a heat-resistant conductive material, and the second conductive layers 113 a and 113 b be formed using an aluminum alloy containing neodymium that has low heat resistance. By such a structure, a low resistance property of aluminum is utilized and generation of a hillock can be reduced. Note that in this embodiment, the source or drain electrode layer 105 a is formed to have a three-layer structure of the first conductive layer 112 a, the second conductive layer 113 a, and the third conductive layer 114 a while the source or drain electrode layer 105 b is formed to have a three-layer structure of the first conductive layer 112 b, the second conductive layer 113 b, and the third conductive layer 114 b; however, the source and drain electrode layers 105 a and 105 b are not limited to this structure. Thus, the source and drain electrode layers 105 a and 105 may have a single-layer structure, a two-layer structure, or a stacked structure of four or more layers.

In addition, without limitation to the thin film transistor having an inverted staggered structure illustrated in FIGS. 1A to 1C, a thin film transistor having an inverted staggered structure in which a channel protective layer 104 is provided over the oxide semiconductor layer 103 may be employed as illustrated in FIG. 12. As the channel protective layer 104, an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide) which is formed by a sputtering method or a vapor phase growth method such as a plasma CVD method or a thermal CVD method can be used. The structure in which the channel protective layer 104 is provided over the oxide semiconductor layer 103 can prevent damage to the channel formation region of the oxide semiconductor layer 103 (e.g., oxidation or reduction in film thickness due to plasma or an etchant in etching at the formation of the oxide semiconductor layer 103) in the manufacturing process. Therefore, reliability of the thin film transistor can be improved. Note that the thin film transistor illustrated in FIG. 12 has the same structure as the thin film transistor illustrated in FIGS. 1A to 1C except that the channel protective layer 104 is formed over the oxide semiconductor layer 103, and reference numerals in FIG. 12 are the same as those used for the thin film transistor illustrated in FIGS. 1A to 1C.

In addition, an inverter circuit can also be formed using two of the above-described bottom-gate thin film transistors.

A driver circuit which is configured to drive a pixel portion is formed using an inverter circuit, a capacitor, a resistor, and the like. When two n-channel TFTs are combined to form an inverter circuit, there are two types of combinations: a combination of an enhancement-type transistor and a depletion-type transistor (hereinafter a circuit formed by such a combination is referred to as an “EDMOS circuit”) and a combination of enhancement-type TFTs (hereinafter a circuit formed by such a combination is referred to as an “EEMOS circuit”). Note that when the threshold voltage of the n-channel TFT is positive, the n-channel TFT is defined as an enhancement-type transistor, while when the threshold voltage of the n-channel TFT is negative, the n-channel TFT is defined as a depletion-type transistor, and this specification follows the above definition.

The pixel portion and the driver circuit are formed over one substrate. In the pixel portion, on and off of voltage application to a pixel electrode are switched using enhancement-type transistors arranged in a matrix. An oxide semiconductor is used for these enhancement-type transistors arranged in the pixel portion. Since the enhancement-type transistor has electric characteristics such as an on/off ratio of 10⁹ or more at a gate voltage of ±20 V, leakage current is small and low power consumption driving can be realized.

FIG. 30A illustrates a cross-sectional structure of the inverter circuit of the driver circuit. Note that a first thin film transistor 430 a and a second thin film transistor 430 b are the inverted staggered thin film transistors illustrated in FIGS. 1A to 1C.

In the thin film transistor 430 a illustrated in FIG. 30A, a first gate electrode layer 401 a is provided over a substrate 400, a gate insulating layer 402 is provided over the first gate electrode layer 401 a, a plurality of oxide clusters 406 are provided over the gate insulating layer 402 in a dispersed manner, a first oxide semiconductor layer 403 a is provided over the gate insulating layer 402 and the oxide clusters 406, and a first wiring 405 a and a second wiring 405 b are provided over the first oxide semiconductor layer 403 a. In a similar manner, also in the thin film transistor 430 b, a second gate electrode layer 401 b is provided over the substrate 400, the gate insulating layer 402 is provided over the second gate electrode layer 401 b, the plurality of oxide clusters 406 are provided over the gate insulating layer 402 in a dispersed manner, a second oxide semiconductor layer 403 b is provided over the gate insulating layer 402 and the oxide clusters 406, and the second wiring 405 b and a third wiring 405 c are provided over the second oxide semiconductor layer 403 b. Here, the second wiring 405 b is directly connected to the second gate electrode layer 401 b through a contact hole 404 formed in the gate insulating layer 402. At least part of the first oxide semiconductor layer 403 a and the second oxide semiconductor layer 403 b are provided in contact with an upper surface of the gate insulating layer 402. Note that as for the structures and materials of the respective portions, the thin film transistor described above is to be referred to.

The first wiring 405 a is a power supply line at a ground potential (a ground power supply line). This power supply line at a ground potential may be a power supply line to which a negative voltage V_(DL) is applied (a negative power supply line). The third wiring 405 c is a power supply line to which a positive voltage V_(DD) is applied (a positive power supply line).

As illustrated in FIG. 30A, the second wiring 405 b which is electrically connected to both the first oxide semiconductor layer 403 a and the second oxide semiconductor layer 403 b is directly connected to the second gate electrode layer 401 b of the second thin film transistor 430 b through the contact hole 404 formed in the gate insulating layer 402. By the direct connection between the second wiring 405 b and the second gate electrode layer 401 b, favorable contact can be obtained, which leads to reduction in contact resistance. In comparison with the case where the second gate electrode layer 401 b and the second wiring 405 b are connected to each other with another conductive film, for example, a transparent conductive film interposed therebetween, reduction in the number of contact holes and reduction in an occupied area due to the reduction in the number of contact holes can be achieved.

Further, FIG. 30C is a plan view of the inverter circuit of the driver circuit. In FIG. 30C, a cross section taken along the chain line Z1-Z2 corresponds to FIG. 30A.

Further, FIG. 30B illustrates an equivalent circuit of the EDMOS circuit. The circuit connection illustrated in FIGS. 30A and 30C corresponds to that illustrated in FIG. 30B. An example in which the first thin film transistor 430 a is an enhancement-type n-channel transistor and the second thin film transistor 430 b is a depletion-type n-channel transistor is illustrated.

In order to manufacture an enhancement-type n-channel transistor and a depletion-type n-channel transistor over one substrate, for example, the first oxide semiconductor layer 403 a and the second semiconductor layer 403 b are formed using different materials or under different conditions. Alternatively, an EDMOS circuit may be formed in such a manner that gate electrodes are provided over and under the oxide semiconductor layer to control the threshold value and a voltage is applied to the gate electrodes so that one of the TFTs is normally on while the other TFT is normally off.

Alternatively, without limitation to the EDMOS circuit, an EEMOS circuit can be manufactured in such a manner that the first thin film transistor 403 a and the second thin film transistor 403 b are enhancement-type n-channel transistors. In that case, the third wiring 405 c and the second gate electrode layer 401 b are connected to each other instead of the connection between the second wiring 405 b and the second gate electrode layer 401 b.

With such a structure, an oxide cluster having higher electrical conductance than an oxide semiconductor layer serving as an active layer is formed between the oxide semiconductor layer and a gate insulating layer; thus, field effect mobility can be improved when a thin film transistor is turned on. Further, increase in off current can be suppressed even when the field effect mobility of the thin film transistor is improved.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments, as appropriate.

Embodiment 2

In this embodiment, a manufacturing process of a display device including the thin film transistor described in Embodiment 1 will be described with reference to FIGS. 2A to 2C, FIGS. 3A to 3C, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIGS. 8A1 and 8A2 and FIGS. 8B1 and 8B2, and FIG. 9. FIGS. 2A to 2C and FIGS. 3A to 3C are cross-sectional views, and FIG. 4, FIG. 5, FIG. 6, and FIG. 7 are plan views. Line A1-A2 and line B1-B2 in each of FIG. 4, FIG. 5, FIG. 6, and FIG. 7 correspond to line A1-A2 and line B1-B2 in each of the cross-sectional views of FIGS. 2A to 2C and FIGS. 3A to 3C, respectively.

First, the substrate 100 is prepared. As the substrate 100, any of the following substrates can be used: non-alkaline glass substrates made of barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, and the like by a fusion method or a float method; ceramic substrates; plastic substrates having heat resistance enough to withstand a process temperature of this manufacturing process; and the like. Alternatively, a metal substrate such as a stainless steel alloy substrate, provided with an insulating film over its surface, may also be used. The substrate 100 may have a size of 320 mm×400 mm, 370 mm×470 mm, 550 mm×650 mm, 600 mm×720 mm, 680 mm×880 mm, 730 mm×920 mm, 1000 mm×1200 mm, 1100 mm×1250 mm, 1150 mm×1300 mm, 1500 mm×1800 mm, 1900 mm×2200 mm, 2160 mm×2460 mm, 2400 mm×2800 mm, 2850 mm×3050 mm, or the like.

In addition, an insulating film as a base film may be formed over the substrate 100. The base film may be formed to have a single-layer structure or a stacked structure of any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a silicon nitride oxide film by a CVD method, a sputtering method, or the like. In the case where a substrate containing mobile ions, such as a glass substrate, is used as the substrate 100, a film containing nitrogen such as a silicon nitride film or a silicon nitride oxide film is used as the base film, whereby the mobile ions can be prevented from entering the oxide semiconductor layer.

Next, a conductive film which is provided to form a gate wiring including the gate electrode layer 101, a capacitor wiring 108, and a first terminal 121 is formed over the entire surface of the substrate 100 by a sputtering method or a vacuum evaporation method. Next, a first photolithography step is performed. A resist mask is formed, and unnecessary portions are removed by etching to form wirings and an electrode (the gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121). At that time, etching is preferably performed so that at least an end portion of the gate electrode layer 101 is tapered for prevention of disconnection. A cross-sectional view at this stage is illustrated in FIG. 2A. Note that a plan view at this stage corresponds to FIG. 4.

The gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121 in a terminal portion can be formed to have a single-layer structure or a stacked structure using the conductive material described in Embodiment 1.

Next, the gate insulating layer 102 is formed over the entire surface of the gate electrode layer 101. The gate insulating layer 102 is formed to a thickness of 50 nm to 250 nm by a CVD method, a sputtering method, or the like.

For example, for the gate insulating layer 102, a silicon oxide film is formed with a thickness of 100 nm by a CVD method or a sputtering method. Needless to say, the gate insulating layer 102 is not limited to such a silicon oxide film and may be a single-layer structure or a stacked structure of any other types of insulating films such as a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and a tantalum oxide film.

Alternatively, as the gate insulating layer 102, a silicon oxide layer can be formed by a CVD method using an organosilane gas. As the organosilane gas, a silicon-containing compound such as tetraethoxysilane (TEOS: chemical formula, Si(OC₂H₅)₄), tetramethylsilane (TMS: chemical formula, Si(CH₃)₄), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC₂H₅)₃), or trisdimethylaminosilane (SiH(N(CH₃)₂)₃) can be used.

Further alternatively, the gate insulating layer 102 may be formed using one kind of oxide, nitride, oxynitride, or nitride oxide of aluminum, yttrium, or hafnium; or a compound including at least two or more kinds of the aforementioned compounds.

Note that in this specification, oxynitride refers to a substance that contains more oxygen atoms than nitrogen atoms and nitride oxide refers to a substance that contains more nitrogen atoms than oxygen atoms. For example, a “silicon oxynitride film” means a film that contains more oxygen atoms than nitrogen atoms, and oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 50 atomic % to 70 atomic %, 0.5 atomic % to 15 atomic %, 25 atomic % to 35 atomic %, and 0.1 atomic % to 10 atomic %, respectively, when they are measured by RBS (Rutherford Backscattering Spectrometry) and HFS (Hydrogen Forward Scattering). Further, a “silicon nitride oxide film” means a film that contains more nitrogen atoms than oxygen atoms, and oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 5 atomic % to 30 atomic %, 20 atomic % to 55 atomic %, 25 atomic % to 35 atomic %, and 10 atomic % to 30 atomic %, respectively, when they are measured by RBS and HFS. Note that percentages of nitrogen, oxygen, silicon, and hydrogen fall within the ranges given above, where the total number of atoms contained in the silicon oxynitride or the silicon nitride oxide is defined as 100 atomic %.

Note that before an oxide semiconductor film which is provided to form the oxide semiconductor layer 103 and the oxide cluster 106 are formed, reverse sputtering by which plasma is generated by introduction of an argon gas in a chamber where the substrate 100 is provided is preferably performed, whereby dust attached to a surface of the gate insulating layer is removed. By reverse sputtering, planarity of the surface of the gate insulating layer 102 can be improved. The reverse sputtering refers to a method in which, without application of voltage to a target side, an RF power source is used for application of voltage to a substrate side in an argon atmosphere and plasma is produced so that a substrate surface is modified. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, or the like may be used. Alternatively, an argon atmosphere to which oxygen, N₂O, or the like is added may be used. Further alternatively, an argon atmosphere to which Cl₂, CF₄, or the like is added may be used. After the reverse sputtering, a first oxide semiconductor film is formed without being exposed to air, whereby dust or moisture can be prevented from attaching to an interface between the oxide semiconductor layer 103 and the oxide cluster 106.

Next, the plurality of oxide clusters 106 are formed over the gate insulating layer 102 in a dispersed manner. As the oxide having electrical conductivity used for the oxide cluster 106, any of indium (In), zinc (Zn), tin (Sn), molybdenum (Mo), or tungsten (W) is included. It is preferable to use indium oxide (InO_(x)), zinc oxide (ZnO_(x)), indium tin oxide (ITO), indium zinc oxide (IZO), molybdenum oxide, or tungsten oxide. However, the electrical conductance of the oxide cluster 106 is made higher than the electrical conductance of the oxide semiconductor layer 103. These oxides having electrical conductivity can be formed by a sputtering method, an evaporation method, a sol-gel method, or the like. The oxide cluster 106 is formed so that a height R thereof is greater than 0 nm and equal to or less than 10 nm, preferably 3 nm to 5 nm inclusive. Here, the height R of the oxide cluster 106 is preferably less than half of the film thickness of the oxide semiconductor layer 103. In a manner similar to that of Embodiment 1, the height R here is the height of the oxide cluster 106 from a reference surface in which a plane of the gate insulating layer 102 and the oxide cluster 106 are in contact with each other.

Next, the oxide semiconductor film which is provided to form the oxide semiconductor layer 103 is formed by a sputtering method without being exposed to air in an atmosphere of rare gas such as an argon gas and an oxygen gas. As the oxide semiconductor film, the oxide semiconductor described in Embodiment 1 can be used, and it is preferable to use an In—Ga—Zn—O-based oxide semiconductor. As specific conditions, an oxide semiconductor target containing In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1) of 8 inches in diameter is used, the distance between the substrate and the target is set to 170 mm, a flow rate ratio of a film formation gas is Ar:O₂=50:5 (sccm), and film formation is performed by sputtering at a pressure of 0.4 Pa, with a direct-current (DC) power source of 0.5 kW, and at room temperature. Further, as the target, Ga₂O₃ and ZnO in a pellet state may be disposed on a disk of 8 inches in diameter which contains In₂O₃. Note that a pulsed direct current (DC) power source is preferably used because dust can be reduced and the thickness distribution is uniform. The thickness of the In—Ga—Zn—O-based non-single-crystal film is set to 10 nm or more, preferably 30 nm to 100 nm inclusive.

In the case where the In—Ga—Zn—O-based non-single-crystal film is formed by a sputtering method, an oxide semiconductor target containing In, Ga, and Zn may be made to contain an insulating impurity. The impurity is insulating oxide typified by silicon oxide, germanium oxide, aluminum oxide, or the like; insulating nitride typified by silicon nitride, aluminum nitride, or the like; or insulating oxynitride such as silicon oxynitride or aluminum oxynitride. For example, the oxide semiconductor target is preferably made to contain SiO₂ at the rate of 0.1 weight % to 10 weight % inclusive, more preferably 1 weight % to 6 weight % inclusive.

The oxide semiconductor is made to contain the insulating impurity, whereby the oxide semiconductor to be formed is made amorphous easily. In addition, in the case where the oxide semiconductor film is subjected to heat treatment, the oxide semiconductor film can be prevented from being crystallized.

In addition to the In—Ga—Zn—O-based oxide semiconductor, a similar effect can be obtained in such a manner that any of the following oxide semiconductors is made to contain the insulating impurity: an In—Sn—Zn—O-based oxide semiconductor; an In—Al—Zn—O-based oxide semiconductor; a Sn—Ga—Zn—O-based oxide semiconductor; an Al—Ga—Zn—O-based oxide semiconductor; a Sn—Al—Zn—O-based oxide semiconductor; an In—Zn—O-based oxide semiconductor; a Sn—Zn—O-based oxide semiconductor; an Al—Zn—O-based oxide semiconductor; an In—O-based oxide semiconductor; a Sn—O-based oxide semiconductor; and a Zn—O-based oxide semiconductor.

For example, in the case where a film of an In—Sn—Zn—O-based oxide semiconductor to which silicon oxide is added is formed by a sputtering method, a target in which In₂O₃, SnO₂, ZnO, and SiO₂ are sintered at a predetermined rate is used as a target thereof. In addition, in the case of the In—Al—Zn—O-based oxide semiconductor to which silicon oxide is added, a film is formed using a target in which In₂O₃, Al₂O₃, ZnO, and SiO₂ are sintered at a predetermined rate as a target thereof.

A chamber used for film formation of the In—Ga—Zn—O-based non-single-crystal film may be the same or different from the chamber in which the reverse sputtering has been performed.

Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case where an insulating film is formed, and a DC sputtering method is mainly used in the case where a metal film is formed.

In addition, there is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be formed to be stacked in the same chamber, or a film of plural kinds of materials can be formed by electric discharge at the same time in the same chamber.

In addition, there are a sputtering apparatus provided with a magnet system inside the chamber and used for a magnetron sputtering method, and a sputtering apparatus used for an ECR sputtering method in which plasma produced with the use of microwaves is used without using glow discharge.

Furthermore, as a film formation method by a sputtering method, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during film formation to form a thin compound film thereof, and a bias sputtering method in which a voltage is also applied to a substrate during film formation.

Next, a second photolithography step is performed. A resist mask is formed, and the In—Ga—Zn—O-based non-single-crystal film is etched. In etching of the In—Ga—Zn—O-based non-single-crystal film, organic acid such as citric acid or oxalic acid can be used for etchant. Here, the In—Ga—Zn—O-based non-single-crystal film is etched by wet etching with the use of ITO-07N (manufactured by Kanto Chemical Co., Inc.) to remove an unnecessary portion. Thus, the In—Ga—Zn—O-based non-single-crystal film is processed into an island-like shape, whereby an oxide semiconductor film 111 which is the In—Ga—Zn—O-based non-single-crystal film is formed. At the same time, the oxide cluster 106 which is formed in a position that does not to overlap with the oxide semiconductor film 111 is etched. The end portion of the oxide semiconductor film 111 is etched into a tapered shape, whereby disconnection of a wiring due to a step shape can be prevented. However, in the case where molybdenum oxide or tungsten oxide is used for the oxide cluster 106, in some cases, the oxide cluster 106 is not removed completely by etching performed on the In—Ga—Zn—O-based non-single-crystal film at the same time. In that case, etching is performed again to remove the remaining oxide cluster 106.

Note that etching here is not limited to wet etching and may be dry etching. As an etching apparatus used for the dry etching, an etching apparatus using a reactive ion etching method (an RIE method) or a dry etching apparatus using a high-density plasma source such as ECR (electron cyclotron resonance) or ICP (inductively coupled plasma) can be used. As a dry etching apparatus by which uniform electric discharge can be obtained over a wider area as compared to an ICP etching apparatus, there is an ECCP (enhanced capacitively coupled plasma) mode apparatus in which an upper electrode is grounded, a high-frequency power source at 13.56 MHz is connected to a lower electrode, and further a low-frequency power source at 3.2 MHz is connected to the lower electrode. This ECCP mode etching apparatus can be applied even when, as the substrate, a substrate, the size of which exceeds 3 m of the tenth generation, is used, for example. A cross-sectional view at this stage is illustrated in FIG. 2B. Note that a plan view at this stage corresponds to FIG. 5.

Next, a third photolithography step is performed to form a resist mask, and unnecessary portions are removed by etching, whereby a contact hole that reaches the wiring or the electrode layer which is formed from the same material as the gate electrode layer 101 is formed. This contact hole is provided for direct contact with the conductive film formed later. For example, in a driving circuit portion, a contact hole is formed when a thin film transistor that is in direct contact with the gate electrode layer and the source or drain electrode layer or a terminal that is electrically connected to a gate wiring of the terminal portion is formed.

Next, over the oxide semiconductor film 111 and the gate insulating layer 102, a first conductive layer 112, a second conductive layer 113, and a third conductive layer 114 which are formed from a metal material is formed by a sputtering method or a vacuum evaporation method. FIG. 2C is a cross-sectional view at this stage.

As the materials of the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114, the conductive material described in Embodiment 1 can be used. In this embodiment, the first conductive layer 112 and the third conductive layer 114 are formed using titanium that is a heat-resistant conductive material, and the second conductive layer 113 is formed using an aluminum alloy containing neodymium. With such a structure, a low resistance property of aluminum is utilized and generation of a hillock can be reduced. Note that in this embodiment, a three-layer structure of the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114 is employed; however, without limitation thereto, a single-layer structure, a two-layer structure, or a stacked structure of four or more layers may be employed.

Next, a fourth photolithography step is performed to form a resist mask 131, and unnecessary portions are removed by etching, whereby source and drain electrode layers 105 a and 105 b, the oxide semiconductor layer 103, and a connection electrode 120 are formed. Wet etching or dry etching is used as an etching method at this time. For example, when the first and third conductive layers 112 and 114 are formed using titanium and the second conductive layer 113 is formed using an aluminum alloy containing neodymium, wet etching can be performed using a hydrogen peroxide solution, heated hydrochloric acid, or a nitric acid solution containing ammonium fluoride as an etchant. For example, the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114 can be etched collectively with the use of KSMF-240 (manufactured by Kanto Chemical Co., Inc.). In this etching step, a region to be exposed in the oxide semiconductor film 111 is also partly etched; thus, the oxide semiconductor layer 103 has a region which is between the source and drain electrode layers 105 a and 105 b and whose thickness is smaller than the thickness of a region overlapping with the source and drain electrode layer 105 a and 105 b. Accordingly, a channel formation region of the oxide semiconductor layer 103 and the oxide cluster 106 overlaps with the small-thickness region of the oxide semiconductor layer 103.

In FIG. 3A, the first conductive layer 112, the second conductive layer 113, the third conductive layer 114, and the oxide semiconductor film 111 can be etched in one step by etching in which a hydrogen peroxide solution, heated hydrochloric acid, or a nitric acid aqueous solution containing ammonium fluoride is used as etchant; therefore, end portions of the source and drain electrode layers 105 a and 105 b and the oxide semiconductor layer 103 are aligned with each other, and a continuous structure can be formed. In addition, wet etching allows the layers to be etched isotropically, so that the end portions of the source and drain electrode layers 105 a and 105 b are recessed from the resist mask 131. Through the aforementioned steps, a thin film transistor 170 which includes the oxide semiconductor layer 103 and the oxide cluster 106 as a channel formation region can be manufactured. A cross-sectional view at this stage is illustrated in FIG. 3A. Note that a plan view at this stage corresponds to FIG. 6.

In a fourth photolithography step, a second terminal 122 made from the same material as the source or drain electrode layers 105 a and 105 b is also left in the terminal portion. Note that the second terminal 122 is electrically connected to a source wiring (a source wiring including the source and drain electrode layers 105 a and 105 b).

In addition, in the terminal portion, the connection electrode 120 is directly connected to the first terminal 121 of the terminal portion through a contact hole formed in the gate insulating layer 102. Note that although not illustrated here, a source or drain wiring of the thin film transistor of the driver circuit is directly connected to the gate electrode through the same steps as the aforementioned steps.

In the above-described fourth photolithography step, two masks are necessary in a step of etching the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114 into an island-like shape and a step of forming the source and drain electrode layers 105 a and 105 b. However, with the use of a resist mask having regions with plural thicknesses (typically, two different thicknesses) which is formed using a multi-tone (high-tone) mask, the number of resist masks can be reduced, resulting in simplified process and lower costs. A photolithography step using a multi-tone mask is described with reference to FIGS. 31A and 31B.

First, from the state of FIG. 2A, the gate insulating layer 102, the oxide cluster 106, the oxide semiconductor film 111, the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114 are formed by the above-described method. Then, a resist mask 132 having regions with a plurality of different thicknesses as illustrated in FIG. 31A is formed over the third conductive layer 114 by light exposure using a multi-tone (high-tone) mask with which transmitted light has a plurality of intensity. The resist mask 132 has a thin film thickness in a region that overlaps with part of the gate electrode layer 101. Next, the oxide semiconductor film 111, the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114 are etched and processed into an island-like shape using the resist mask 132 to form an oxide semiconductor layer 140, a conductive layer 115, and a second terminal 124. A cross-sectional view at this stage corresponds to FIG. 31A.

Next, the resist mask 132 is subjected to ashing to form the resist mask 131. As illustrated in FIG. 31B, the resist mask 131 is reduced in area and thickness by ashing, and the region thereof having a thin thickness is removed.

Lastly, the oxide semiconductor layer 140, the conductive layer 115, and the second terminal 124 are etched using the resist mask 131 to form the oxide semiconductor layer 103, the source and drain electrode layers 105 a and 105 b, and the second terminal 122. The resist mask 131 is reduced in area and thickness, whereby the oxide semiconductor layer 103, the source and drain electrode layers 105 a and 105 b, and the end portion of the second terminal 122 are also etched. A cross-sectional view at this stage corresponds to FIG. 31B. Note that after a protective insulating layer 107 is formed in a subsequent step, the gate insulating layer 102 and the protective insulating layer 107 are etched to form a contact hole, whereby a transparent conductive film is formed to connect the first terminal 121 and an FPC to each other. In an aforementioned manner, the thin film transistor 170 can be manufactured using a multi-tone mask.

Next, after the resist mask 131 is removed, heat treatment is preferably performed at 200° C. to 700° C., typically, 250° C. to 500° C. Here, heat treatment is performed in a nitrogen atmosphere in a furnace at 350° C. for 1 hour. Through this heat treatment, rearrangement at the atomic level occurs in the In—Ga—Zn—O-based non-single-crystal film. Because strain which inhibits carrier transport is released by the heat treatment, the heat treatment (including optical annealing) is important. Note that there is no particular limitation on the timing of heat treatment as long as it is performed after formation of the In—Ga—Zn—O-based non-single-crystal film, and, for example, heat treatment may be performed after formation of a pixel electrode. Alternatively, the electrical conductance of the oxide cluster 106 can be improved by crystallization of the oxide cluster 106 through the above heat treatment.

Further, the exposed channel formation region of the oxide semiconductor layer 103 may be subjected to oxygen radical treatment. The oxygen radical treatment is performed, whereby the thin film transistor can be normally off. In addition, the radical treatment can repair damage due to the etching of the oxide semiconductor layer 103. The radical treatment is preferably performed in an atmosphere of O₂ or N₂O, and preferably an atmosphere of N₂, He, or Ar each containing oxygen. Alternatively, the radical treatment may be performed in an atmosphere in which Cl₂ and CF₄ are added to the above atmosphere. Note that the radical treatment is preferably performed with no bias applied.

Next, the protective insulating layer 107 is formed to cover the thin film transistor 170. For the protective insulating layer 107, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or the like which is obtained by a sputtering method or the like can be used.

Then, a fifth photolithography step is performed to form a resist mask, and the protective insulating layer 107 is etched to form a contact hole 125 that reaches the drain electrode layer 105 b. In addition, by the etching here, a contact hole 127 that reaches the second terminal 122 and a contact hole 126 that reaches the connection electrode 120 are also formed. A cross-sectional view at this stage is illustrated in FIG. 3B.

Then, after the resist mask is removed, a transparent conductive film is formed. The transparent conductive film is formed using indium oxide (In₂O₃), an alloy of indium oxide and tin oxide (In₂O₃—SnO₂, abbreviated to ITO), or the like by a sputtering method, a vacuum evaporation method, or the like. Etching treatment of such a material is performed with a hydrochloric acid based solution. Instead, because a residue tends to be generated particularly in etching of ITO, an alloy of indium oxide and zinc oxide (In₂O₃—ZnO) may be used in order to improve etching processability.

Next, a sixth photolithography step is performed to form a resist mask, and unnecessary portions are removed by etching, whereby a pixel electrode layer 110 is formed.

Further, in this sixth photolithography step, the capacitor wiring 108 and the pixel electrode layer 110 together form a storage capacitor with the use of the gate insulating layer 102 and the protective insulating layer 107 in a capacitor portion as a dielectric.

In addition, in this sixth photolithography step, the first terminal and the second terminal are covered with the resist mask, and transparent conductive films 128 and 129 are left in the terminal portion. The transparent conductive films 128 and 129 serve as electrodes or wirings that are used for connection with an FPC. The transparent conductive film 128 formed over the connection electrode 120 that is directly connected to the first terminal 121 serves as a terminal electrode for connection which functions as an input terminal for the gate wiring. The transparent conductive film 129 formed over the second terminal 122 serves as a terminal electrode for connection which functions as an input terminal for the source wiring.

Then, the resist mask is removed, and a cross-sectional view at this stage is illustrated in FIG. 3C. Note that a plan view at this stage corresponds to FIG. 7.

Further, FIGS. 8A1 and 8A2 are a cross-sectional view of a gate wiring terminal portion at this stage and a plan view thereof, respectively. FIG. 8A1 is a cross-sectional view taken along line C1-C2 of FIG. 8A2. In FIG. 8A1, a transparent conductive film 155 formed over a protective insulating film 154 is a terminal electrode for connection which functions as an input terminal. Furthermore, in FIG. 8A1, in the terminal portion, the first terminal 151 formed from the same material as the gate wiring and a connection electrode 153 formed from the same material as the source wiring overlap with each other through a contact hole provided in the gate insulating layer 152 so that the first terminal 151 and the connection electrode 153 are in direct contact with each other to form conduction therebetween. In addition, the connection electrode 153 and the transparent conductive film 155 are in direct contact with each other through a contact hole provided in the protective insulating film 154 to form conduction therebetween.

Further, FIGS. 8B1 and 8B2 are a cross-sectional view of a source wiring terminal portion at this stage and a plan view thereof, respectively. In addition, FIG. 8B1 corresponds to a cross-sectional view taken along line D1-D2 in FIG. 8B2. In FIG. 8B1, the transparent conductive film 155 formed over the protective insulating film 154 is a terminal electrode for connection which functions as an input terminal. Furthermore, in FIG. 8B1, in the terminal portion, an electrode 156 formed from the same material as the gate wiring is located below and overlapped with a second terminal 150, which is electrically connected to the source wiring, with the gate insulating layer 152 interposed therebetween. The electrode 156 is not electrically connected to the second terminal 150. When the electrode 156 is set to, for example, floating, GND, or 0 V such that the potential of the electrode 156 is different from the potential of the second terminal 150, a capacitor which is provided to prevent noise or static electricity can be formed. In addition, the second terminal 150 is electrically connected to the transparent conductive film 155 with the protective insulating film 154 interposed therebetween.

A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. Also in the terminal portion, the first terminal at the same potential as the gate wiring, the second terminal at the same potential as the source wiring, a third terminal at the same potential as the capacitor wiring, and the like are each arranged in plurality. There is no particular limitation on the number of each of the terminals, and the number of the terminals may be determined by a practitioner as appropriate.

Through these six photolithography steps, the storage capacitor and a pixel thin film transistor portion including the thin film transistor 170 which is a bottom-gate n-channel thin film transistor can be completed using the six photomasks. The pixel thin film transistor portion and storage capacitor are arranged in a matrix corresponding to respective pixels so that a pixel portion is formed, whereby one of substrates which is provided to manufacture an active matrix display device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

When an active matrix liquid crystal display device is manufactured, an active matrix substrate and a counter substrate provided with a counter electrode are fixed to each other with a liquid crystal layer interposed therebetween. Note that a common electrode electrically connected to the counter electrode on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. This fourth terminal is provided so that the common electrode is fixed to a predetermined potential such as GND or 0 V.

Further, this embodiment is not limited to a pixel structure in FIG. 7, and an example of a plan view different from FIG. 7 is illustrated in FIG. 9. FIG. 9 illustrates an example in which a capacitor wiring is not provided and a storage capacitor is formed with the pixel electrode layer 110 and a gate wiring of an adjacent pixel which are overlapped with each other with a protective insulating film and a gate insulating layer interposed therebetween. In this case, the capacitor wiring and the third terminal connected to the capacitor wiring can be omitted. Note that in FIG. 9, portions similar to those in FIG. 7 are denoted by the same reference numerals.

In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix are driven, whereby a display pattern is formed on a screen. Specifically, a voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, whereby a liquid crystal layer provided between the pixel electrode and the counter electrode is optically modulated and this optical modulation is recognized as a display pattern by an observer.

In displaying moving images, a liquid crystal display device has a problem in that a long response time of liquid crystal molecules themselves causes afterimages or blurring of moving images. In order to improve the moving-image characteristics of a liquid crystal display device, a driving method called black insertion is employed in which black is displayed on the whole screen every other frame period.

Alternatively, a driving method called double-frame rate driving may be employed in which a vertical synchronizing frequency is 1.5 times or more, preferably, 2 times or more as high as a usual vertical synchronizing frequency, whereby the moving-image characteristics are improved.

Further alternatively, in order to improve the moving-image characteristics of a liquid crystal display device, a driving method may be employed in which a plurality of LEDs (light-emitting diodes) or a plurality of EL light sources are used to form a surface light source as a backlight, and each light source of the surface light source is independently driven in a pulsed manner in one frame period. As the surface light source, three or more kinds of LEDs may be used, or an LED emitting white light may be used. Since a plurality of LEDs can be controlled independently, the light emission timing of LEDs can be synchronized with the timing at which a liquid crystal layer is optically modulated. According to this driving method, LEDs can be partly turned off; therefore, an effect of reducing power consumption can be obtained particularly in the case of displaying an image having a large part on which black is displayed.

These driving methods are combined, whereby the display characteristics of a liquid crystal display device, such as moving-image characteristics, can be improved as compared to those of conventional liquid crystal display devices.

The n-channel transistor obtained in this embodiment includes an In—Ga—Zn—O-based non-single-crystal film in a channel formation region and has good dynamic characteristics. Thus, these driving methods can be applied in combination with the n-channel transistor of this embodiment.

When a light-emitting display device is manufactured, one electrode (also referred to as a cathode) of an organic light-emitting element is set to a low power supply potential such as GND or 0 V; therefore, a terminal portion is provided with a fourth terminal which is provided to set the cathode to a low power supply potential such as GND or 0 V. In addition, when a light-emitting display device is manufactured, a power supply line is provided in addition to a source wiring and a gate wiring. Therefore, a terminal portion is provided with a fifth terminal electrically connected to the power supply line.

With such a structure, in a thin film transistor including an oxide semiconductor layer, an oxide cluster having higher electrical conductance than an oxide semiconductor layer serving as an active layer is formed between the oxide semiconductor layer and a gate insulating layer; thus, field effect mobility can be improved when the thin film transistor is turned on. Further, increase in off current can be suppressed even when the field effect mobility of the thin film transistor is improved.

A display device with high electric characteristics and high reliability can be provided using the thin film transistor in a pixel portion or a driver circuit portion of the display device.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments, as appropriate.

Embodiment 3

In this embodiment, a thin film transistor having a different shape from the thin film transistor described in Embodiment 1 is described with reference to FIG. 10.

A thin film transistor having a bottom-gate structure of this embodiment is illustrated in FIG. 10. In the thin film transistor illustrated in FIG. 10, the gate electrode layer 101 is provided over the substrate 100, the gate insulating layer 102 is provided over the gate electrode layer 101, the plurality of oxide clusters 106 is provided over the gate insulating layer 102 in a dispersed manner, the oxide semiconductor layer 103 is provided over the gate insulating layer 102 and the plurality of oxide clusters 106, buffer layers 301 a and 301 b are provided over the oxide semiconductor layer 103, and the source and drain electrode layers 105 a and 105 b are provided over the buffer layers 301 a and 301 b. Here, the oxide semiconductor layer 103 and the source electrode layer 105 are electrically connected to each other with the buffer layer 301 a interposed therebetween, and the oxide semiconductor layer 103 and the drain electrode layer 105 b are electrically connected to each other with the buffer layer 301 b interposed therebetween. The source or drain electrode layer 105 a has a three-layer structure of the first conductive layer 112 a, the second conductive layer 113 a, and the third conductive layer 114 a while the source or drain electrode layer 105 b has a three-layer structure of the first conductive layer 112 b, the second conductive layer 113 b, and the third conductive layer 114 b. That is, the thin film transistor illustrated in FIG. 10 has a structure in which the buffer layers 301 a and 301 b are provided between the oxide semiconductor layer 103 and the source and drain electrode layers 105 a and 105 b in the thin film transistor illustrated in FIGS. 1A to 1C in Embodiment 1.

In a manner similar to that of formation of the oxide semiconductor layer 103, the buffer layers 301 a and 301 b which function as a source and drain regions are preferably formed using an In—Ga—Zn—O-based non-single-crystal film which is an oxide semiconductor film containing In, Ga, and Zn. In this embodiment, the In—Ga—Zn—O-based non-single-crystal film which is an oxide semiconductor film containing In, Ga, and Zn is used for the oxide semiconductor layer 103. Note that the buffer layers 301 a and 301 b have n-type conductivity and higher electrical conductance than the oxide semiconductor layer 103. Further, the buffer layers 301 a and 301 b are In—Ga—Zn—O-based non-single-crystal films, and include at least an amorphous component. In some cases, the buffer layers 301 a and 301 b include crystal grains (nanocrsytals) in the amorphous structure. The crystal grains (nanocrystals) each have a diameter of 1 nm to 10 nm, typically approximately 2 nm to 4 nm.

The In—Ga—Zn—O-based non-single-crystal film used for the buffer layers 301 a and 301 b is formed by a sputtering method. As specific conditions, an oxide semiconductor target containing In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1) of 8 inches in diameter is used, the distance between the substrate and the target is set to 170 mm, a flow rate ratio of a film formation gas is Ar:O₂=50:1 (sccm), and film formation is performed by sputtering at a pressure of 0.4 Pa, with a direct-current (DC) power source of 0.5 kW, and at room temperature.

Note that the conditions of forming the In—Ga—Zn—O-based non-single-crystal film used for the buffer layers 301 a and 301 b are different from those of forming the In—Ga—Zn—O-based non-single-crystal film used for the oxide semiconductor layer. For example, the proportion of the flow rate of the oxygen gas in the film formation gas for forming the In—Ga—Zn—O-based non-single-crystal film used for the buffer layers 301 a and 301 b is made lower than that of the flow rate of the oxygen gas in the film formation gas for forming the In—Ga—Zn—O-based non-single-crystal film used for the oxide semiconductor layer. In addition, the In—Ga—Zn—O-based non-single-crystal film used for the buffer layers 301 a and 301 b may be formed in an atmosphere of rare gas such as an argon gas without containing an oxygen gas.

The thickness of the In—Ga—Zn—O-based non-single-crystal film used for the buffer layers 301 a and 301 b is set to 5 nm to 20 nm Needless to say, when the film includes crystal grains, the size of the crystal grains does not exceed the thickness of the film. In this embodiment, the thickness of the In—Ga—Zn—O-based non-single-crystal film used for the buffer layers 301 a and 301 b is set to 5 nm.

The buffer layers 301 a and 301 b may contain an impurity element imparting n-type conductivity. As an example of the impurity element, it is possible to use, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, or lead. In the case where magnesium, aluminum, titanium, or the like is contained in the buffer layers, there is an effect of blocking oxygen, and the like, so that the oxygen concentration of the oxide semiconductor layer can be kept within an optimal range by heat treatment or the like after the film formation.

The carrier concentration of the buffer layers is preferably 1×10¹⁸/cm³ or higher (and 1×10²²/cm³ or lower).

With such a structure, provision of the buffer layers 301 a and 301 b can make thermal stability improved more than formation of Schottky junction do, between the oxide semiconductor layer and the source and drain electrode layers 105 a and 105 b, whereby operating characteristics of the thin film transistor can be stabilized. In addition, because of high electrical conductivity, favorable mobility can be kept even when high drain voltage is applied.

Note that as for a structure and materials of the thin film transistor of this embodiment other than the buffer layers 301 a and 301 b, Embodiment 1 is to be referred to.

A manufacturing process of the thin film transistor of this embodiment is almost similar to the manufacturing process of the thin film transistor described in Embodiment 2. First, by the method described in Embodiment 2, steps up to forming the oxide semiconductor film which is provided to form the oxide semiconductor layer 103 are performed. Following the above steps, the oxide semiconductor film which is provided to form the buffer layers 301 a and 301 b is formed by sputtering with the use of the above method. Next, by the second photolithography step, in a manner similar to that of formation of the oxide semiconductor film 111, the oxide semiconductor film which is provided to form the buffer layers 301 a and 301 b is etched into an island-like shape, whereby an oxide semiconductor film 302 is formed (see FIG. 11A). Then, by the method described in Embodiment 2, the steps up to forming the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114 are performed (see FIG. 11B). Next, by the fourth photolithography step, in a manner similar to that of formation of the source and drain electrode layers 105 a and 105 b and the oxide semiconductor layer 103, the oxide semiconductor film 302 is etched to form the buffer layers 301 a and 301 b (see FIG. 11C). Subsequent steps are similar to those in Embodiment 2.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments, as appropriate.

Embodiment 4

In this embodiment, an example of manufacturing at least part of a driver circuit and a thin film transistor arranged in a pixel portion over one substrate in a display device which is an example of a semiconductor device will be described below.

The thin film transistor in the pixel portion is formed in accordance with any of Embodiments 1 to 3. The thin film transistor described in any of Embodiments 1 to 3 is an n-channel TFT; therefore, part of a driver circuit which can be formed using an n-channel TFT is formed over the same substrate as the thin film transistor of the pixel portion.

FIG. 14A illustrates an example of a block diagram of an active matrix liquid crystal display device which is an example of a semiconductor device. The display device illustrated in FIG. 14A includes, over a substrate 5300, a pixel portion 5301 having a plurality of pixels that is each provided with a display element, a scan-line driver circuit 5302 that selects each pixel, and a signal-line driver circuit 5303 that controls a video signal input to a selected pixel.

The pixel portion 5301 is connected to the signal-line driver circuit 5303 with a plurality of signal lines S1 to Sm (not illustrated) extending in a column direction from the signal-line driver circuit 5303 and connected to the scan-line driver circuit 5302 with a plurality of scan lines G1 to Gn (not illustrated) extending in a row direction from the scan-line driver circuit 5302. The pixel portion 5301 includes a plurality of pixels (not illustrated) arranged in a matrix so as to correspond to the signal lines S1 to Sm and the scan lines G1 to Gn. In addition, each of the pixels is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scan line Gi (any one of the scan lines G1 to Gn).

The thin film transistor described in any of Embodiments 1 to 3 is an n-channel TFT, and a signal-line driver circuit including an n-channel TFT is described with reference to FIG. 15.

The signal-line driver circuit illustrated in FIG. 15 includes a driver IC 5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first thin film transistor 5603 a, a second thin film transistor 5603 b, and a third thin film transistor 5603 c.

The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to three signal lines (a signal line Sm−2, a signal line Sm−1, and a signal line Sm (m=3M)) through the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c. For example, a wiring 5621_J of the J-th column (any one of the wirings 5621_1 to 5621_M) is connected to a signal line Sj−2, a signal line Sj−1, and a signal line Sj (j=3J) through the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c of a switch group 5602_J.

Note that a signal is inputted to each of the first wiring 5611, the second wiring 5612, and the third wiring 5613.

Note that the driver IC 5601 is preferably formed using a single crystal semiconductor. Further, the switch groups 5602_1 to 5602_M are preferably formed over the same substrate as the pixel portion. Therefore, the driver IC 5601 is preferably connected to the switch groups 5602_1 to 5602_M through an FPC or the like. Alternatively, a single crystal semiconductor layer may be provided over the same substrate as the pixel portion by a method such as bonding to form the driver IC 5601.

Next, operation of the signal-line driver circuit illustrated in FIG. 15 is described with reference to a timing chart of FIG. 16. FIG. 16 illustrates the timing chart where the scan line Gi in the i-th row is selected. Further, a selection period of the scan line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal-line driver circuit in FIG. 15 operates similarly to that in FIG. 16 even when a scan line of another row is selected.

Note that the timing chart of FIG. 16 illustrates the case where the wiring 5621_J in the J-th column is connected to the signal line Sj−2, the signal line Sj−1, and the signal line Sj through the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c.

The timing chart of FIG. 16 illustrates timing when the scan line Gi in the i-th row is selected, timing 5703 a of on/off of the first thin film transistor 5603 a, timing 5703 b of on/off of the second thin film transistor 5603 b, timing 5703 c of on/off of the third thin film transistor 5603 c, and a signal 5721_J inputted to the wiring 5621_J in the J-th column.

In the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, different video signals are inputted to the wirings 5621_1 to 5621_M. For example, a video signal inputted to the wiring 5621_J in the first sub-selection period T1 is inputted to the signal line Sj−2, a video signal inputted to the wiring 5621_J in the second sub-selection period T2 is inputted to the signal line Sj−1, and a video signal inputted to the wiring 5621_J in the third sub-selection period T3 is inputted to the signal line Sj. The video signals inputted to the wiring 5621_J in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 are denoted by Data_j−2, Data_j−1, and Data_j.

As illustrated in FIG. 16, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603 b and the third thin film transistor 5603 c are turned off. At this time, Data_j−2 inputted to the wiring 5621_J is inputted to the signal line Sj−2 through the first thin film transistor 5603 a. In the second sub-selection period T2, the second thin film transistor 5603 b is turned on, and the first thin film transistor 5603 a and the third thin film transistor 5603 c are turned off. At this time, Data_j−1 inputted to the wiring 5621_J is inputted to the signal line Sj−1 through the second thin film transistor 5603 b. In the third sub-selection period T3, the third thin film transistor 5603 c is turned on, and the first thin film transistor 5603 a and the second thin film transistor 5603 b are turned off. At this time, Data_j inputted to the wiring 5621_J is inputted to the signal line Sj through the third thin film transistor 5603 c.

As described above, in the signal-line driver circuit of FIG. 15, one gate selection period is divided into three; thus, video signals can be inputted to three signal lines through one wiring 5621 in one gate selection period. Therefore, in the signal-line driver circuit of FIG. 15, the number of connections between the substrate provided with the driver IC 5601 and the substrate provided with the pixel portion can be reduced to approximately one third of the number of signal lines. The number of connections is reduced to approximately one third of the number of signal lines, so that the reliability, yield, and the like of the signal-line driver circuit of FIG. 15 can be improved.

Note that there is no particular limitation on the arrangement, number, driving method, and the like of the thin film transistor as long as one gate selection period is divided into a plurality of sub-selection periods and video signals are inputted to a plurality of signal lines from one wiring in each of the plurality of sub-selection periods, as illustrated in FIG. 15.

For example, when video signals are inputted to three or more signal lines from one wiring in each of three or more sub-selection periods, a thin film transistor and a wiring which is configured to control the thin film transistor may be added. Note that when one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes shorter. Therefore, one gate selection period is preferably divided into two or three sub-selection periods.

As another example, as illustrated in a timing chart of FIG. 17, one gate selection period may be divided into a pre-charge period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. Further, the timing chart of FIG. 17 illustrates timing when the scan line Gi in the i-th row is selected, timing 5803 a of on/off of the first thin film transistor 5603 a, timing 5803 b of on/off of the second thin film transistor 5603 b, timing 5803 c of on/off of the third thin film transistor 5603 c, and a signal 5821_J inputted to the wiring 5621_J in the J-th column. As illustrated in FIG. 17, the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c are turned on in the pre-charge period Tp. At this time, a pre-charge voltage V_(p) inputted to the wiring 5621_J is inputted to each of the signal line Sj−2, the signal line Sj−1, and the signal line Sj through the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c. In the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603 b and the third thin film transistor 5603 c are turned off. At this time, Data_j−2 inputted to the wiring 5621_J is inputted to the signal line Sj−2 through the first thin film transistor 5603 a. In the second sub-selection period T2, the second thin film transistor 5603 b is turned on, and the first thin film transistor 5603 a and the third thin film transistor 5603 c are turned off. At this time, Data_j−1 inputted to the wiring 5621_J is inputted to the signal line Sj−1 through the second thin film transistor 5603 b. In the third sub-selection period T3, the third thin film transistor 5603 c is turned on, and the first thin film transistor 5603 a and the second thin film transistor 5603 b are turned off. At this time, Data_j inputted to the wiring 5621_J is inputted to the signal line Sj through the third thin film transistor 5603 c.

As described above, in the signal-line driver circuit of FIG. 15, to which the timing chart of FIG. 17 is applied, a signal line can be pre-charged by providing a pre-charge period before sub-selection periods. Thus, a video signal can be written to a pixel at high speed. Note that portions in FIG. 17 similar to those in FIG. 16 are denoted by the same reference numerals, and detailed description of the same portions and portions having similar functions is omitted.

In addition, a configuration of the scan-line driver circuit is described. The scan-line driver circuit includes a shift register and a buffer. Moreover, a level shifter may be included in some cases. In the scan-line driver circuit, when a clock signal (CLK) and a start pulse signal (SP) are inputted to the shift register, a selection signal is generated. The generated selection signal is buffered and amplified by the buffer, and the resulting signal is supplied to a corresponding scan line. Gate electrodes of transistors in pixels of one line are connected to the scan line. Further, since the transistors in the pixels of one line have to be turned on all at once, a buffer which can feed a large amount of current is used.

One mode of the shift register used for part of the scan-line driver circuit is described with reference to FIG. 18 and FIG. 19.

FIG. 18 illustrates a circuit configuration of the shift register. The shift register illustrated in FIG. 18 includes a plurality of flip-flops, flip-flops 5701_1 to 5701 _(—) n. Further, the shift register operates with input of a first clock signal, a second clock signal, a start pulse signal, and a reset signal.

The connection relation of the shift register illustrated in FIG. 18 is described. The flip-flop 5701_1 of a first stage is connected to a first wiring 5711, a second wiring 5712, a fourth wiring 5714, a fifth wiring 5715, a seventh wiring 5717_1, and a seventh wiring 5717_2. The flip-flop 5701_2 of a second stage is connected to a third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 57172, and a seventh wiring 5717_3.

In a similar manner, a flip-flop 5701 _(—) i (any one of the flip-flops 5701_1 to 5701 _(—) n) of an i-th stage is connected to one of the second wiring 5712 and the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, a seventh wiring 5717 _(—) i−1, a seventh wiring 5717 _(—) i, and a seventh wiring 5717 _(—) i+1. Here, when the “i” is an odd number, the flip-flop 5701 _(—) i of the i-th stage is connected to the second wiring 5712; when the “i” is an even number, the flip-flop 5701 _(—) i of the i-th stage is connected to the third wiring 5713.

The flip-flop 5701 _(—) n of an n-th stage is connected to one of the second wiring 5712 and the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, a seventh wiring 5717 _(—) n−1, a seventh wiring 5717 _(—) n, and a sixth wiring 5716.

Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Further, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as a first power supply line and a second power supply line, respectively.

Next, FIG. 19 illustrates details of the flip-flop in FIG. 18. A flip-flop illustrated in FIG. 19 includes a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and an eighth thin film transistor 5578. Each of the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 is an n-channel transistor and is turned on when the gate-source voltage (V_(gs)) exceeds the threshold voltage (V_(th)).

In addition, the flip-flop illustrated in FIG. 19 includes a first wiring 5501, a second wiring 5502, a third wiring 5503, a fourth wiring 5504, a fifth wiring 5505, and a sixth wiring 5506.

Although the example in which all the thin film transistors are enhancement-type n-channel transistors is described here, there is no limitation to this example. For example, the driver circuit can be driven even with the use of a depletion-type n-channel transistor.

Next, connection structures of the flip-flop illustrated in FIG. 18 is described below.

A first electrode (one of a source electrode and a drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504. A second electrode (the other of the source electrode and the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506. A second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

A first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, and a second electrode of the third thin film transistor 5573 is connected to a gate electrode of the second thin film transistor 5572. A gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505.

A first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506. A second electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572. A gate electrode of the fourth thin film transistor 5574 is connected to a gate electrode of the first thin film transistor 5571.

A first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505. A second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501.

A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. A second electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5572.

A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. A second electrode of the seventh thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502.

A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. A second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572. A gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 5501.

Note that the points at which the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574, the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576, and the second electrode of the seventh thin film transistor 5577 are connected are each referred to as a node 5543. The points at which the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 are connected are each referred to as a node 5544.

Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5504 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Further, the fifth wiring 5505 and the sixth wiring 5506 may be referred to as a first power supply line and a second power supply line, respectively.

In the flip-flop 5701 _(—) i of the i-th stage, the first wiring 5501 in FIG. 19 is connected to the seventh wiring 5717 _(—) i−1 in FIG. 18. The second wiring 5502 in FIG. 19 is connected to the seventh wiring 5717 _(—) i+1 in FIG. 18. The third wiring 5503 in FIG. 19 is connected to the seventh wiring 5717 _(—) i. The sixth wiring 5506 in FIG. 19 is connected to the fifth wiring 5715.

If the “i” is an odd number, the fourth wiring 5504 in FIG. 19 is connected to the second wiring 5712 in FIG. 18; if the “i” is an even number, the fourth wiring 5504 in FIG. 19 is connected to the third wiring 5713 in FIG. 18. In addition, the fifth wiring 5505 in FIG. 19 is connected to the fourth wiring 5714 in FIG. 18.

Note that in the flip-flop 5701_1 of the first stage, the first wiring 5501 in FIG. 19 is connected to the first wiring 5711 in FIG. 18. In addition, in the flip-flop 5701 _(—) n of the n-th stage, the second wiring 5502 in FIG. 19 is connected to the sixth wiring 5716 in FIG. 18.

Alternatively, the signal line driver circuit and the scan line driver circuit can be formed using only the n-channel TFTs described in Embodiments 1 to 3. The n-channel TFT described in Embodiments 1 to 3 has high mobility, and thus a driving frequency of a driver circuit can be increased. Further, parasitic capacitance of the n-channel TFT described in Embodiments 1 to 3 is reduced because of source and drain regions which are formed using an In—Ga—Zn—O-based non-single-crystal film; thus, frequency characteristics (referred to as f characteristics) of the n-channel TFT are high. For example, the scan-line driver circuit including the n-channel TFT described in Embodiments 1 to 3 can operate at high speed; therefore, it is possible to increase the frame frequency or to achieve insertion of a black screen, for example.

In addition, when the channel width of the transistor in the scan-line driver circuit is increased or a plurality of scan-line driver circuits are provided, for example, much higher frame frequency can be realized. When a plurality of scan line driver circuits are provided, a scan-line driver circuit which is configured to drive scan lines of even-numbered rows is provided on one side and a scan-line driver circuit to drive scan lines of odd-numbered rows is provided on the opposite side, whereby increase in frame frequency can be realized. Furthermore, the use of the plurality of scan-line driver circuits to output signals to the same scan line is advantageous in increasing the size of a display device.

Further, in the case of manufacturing an active matrix light-emitting display device which is an example of a semiconductor device, a plurality of scan-line driver circuits are preferably arranged because a plurality of thin film transistors are arranged in at least one pixel. FIG. 14B illustrates an example of a block diagram of an active matrix light-emitting display device.

The light-emitting display device illustrated in FIG. 14B includes, over a substrate 5400, a pixel portion 5401 including a plurality of pixels each provided with a display element, a first scan-line driver circuit 5402 and a second scan-line driver circuit 5404 that selects a pixel, and a signal-line driver circuit 5403 that controls a video signal inputted to the selected pixel.

In the case where the video signal inputted to a pixel of the light-emitting display device illustrated in FIG. 14B is a digital signal, the pixel is put in a light-emitting state or a non-light-emitting state by switching on/off of a transistor. Thus, grayscale can be displayed using an area-ratio grayscale method or a time grayscale method. An area-ratio grayscale method refers to a driving method by which one pixel is divided into a plurality of sub-pixels and the respective sub-pixels are driven separately based on video signals so that grayscale is displayed. Further, a time grayscale method refers to a driving method by which a period during which a pixel is in a light-emitting state is controlled so that grayscale is displayed.

Since the response time of light-emitting elements is higher than that of liquid crystal elements or the like, the light-emitting elements are suitable for a time grayscale method than the liquid crystal element. Specifically, in the case of displaying with a time gray scale method, one frame period is divided into a plurality of sub-frame periods. Then, in accordance with video signals, the light-emitting element in the pixel is put in a light-emitting state or a non-light-emitting state in each sub-frame period. One frame period is divided into a plurality of sub-frame periods, whereby the total length of time, in which pixels actually emit light in one frame period, can be controlled with video signals to display grayscale.

Note that in the example of the light-emitting display device illustrated in FIG. 14B, when two switching TFTs are arranged in one pixel, the first scan-line driver circuit 5402 generates a signal which is inputted to a first scan line serving as a gate wiring of one of the two switching TFTs, and the second scan-line driver circuit 5404 generates a signal which is inputted to a second scan line serving as a gate wiring of the other of the two switching TFTs. However, one scan-line driver circuit may generate both the signal which is inputted to the first scan line and the signal which is inputted to the second scan line. In addition, for example, there is a possibility that a plurality of scan lines used for controlling the operation of the switching element are provided in each pixel, depending on the number of the switching TFTs included in one pixel. In this case, one scan-line driver circuit may generate all signals that are inputted to the plurality of scan lines, or a plurality of scan-line driver circuits may generate signals that are inputted to the plurality of scan lines.

Also in the light-emitting display device, part of the driver circuit that can include the n-channel TFTs among driver circuits can be formed over the same substrate as the thin film transistors of the pixel portion. Alternatively, the signal-line driver circuit and the scan-line driver circuit can be formed using only the n-channel TFTs described in Embodiments 1 to 3.

Moreover, the above-described driver circuits may be used for electronic paper that drives electronic ink using an element electrically connected to a switching element, without being limited to applications to a liquid crystal display device or a light-emitting display device. The electronic paper is also referred to as an electrophoretic display device (an electrophoretic display) and is advantageous in that it has the same level of readability as plain paper, it has less power consumption than other display devices, and it can be made thin and lightweight.

Electrophoretic displays can have various modes. Electrophoretic displays contain a plurality of microcapsules dispersed in a solvent or a solute, each microcapsule containing first particles which are positively charged and second particles which are negatively charged. By application of an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to each other and only the color of the particles gathering on one side is displayed. Note that the first particles or the second particles contain a colorant, and does not move without an electric field. Moreover, a color of the first particles is different from a color of the second particles (the particles may also be colorless).

Thus, an electrophoretic display is a display that utilizes a so-called dielectrophoretic effect in which a substance having a high dielectric constant moves to a high-electric field region.

A solution in which the above microcapsules are dispersed in a solvent is referred to as electronic ink. This electronic ink can be printed on a surface of glass, plastic, cloth, paper, or the like. Furthermore, with the use of a color filter or particles having a coloring matter, color display can also be achieved.

In addition, if a plurality of the above microcapsules are arranged as appropriate over an active matrix substrate so as to be interposed between two electrodes, an active matrix display device can be completed, and display can be performed by application of an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors described in Embodiment 2 can be used.

Note that the first particles and the second particles in the microcapsule may be formed from one of a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, and a magnetophoretic material, or a composite material thereof.

Through the aforementioned steps, a highly reliable light-emitting display device as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments, as appropriate.

Embodiment 5

The thin film transistor described in any of Embodiments 1 to 3 can be manufactured, and the thin film transistor can be used for a pixel portion and further for a driver circuit, so that a semiconductor device having a display function (also referred to as a display device) can be manufactured. Moreover, the thin film transistor described in any of Embodiments 1 to 3 can be used for part of a driver circuit or an entire driver circuit formed over the same substrate as a pixel portion, so that a system-on-panel can be formed.

The display device includes a display element. A liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used as the display element. A light-emitting element includes, in its scope, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic electroluminescent (EL) element, an organic EL element, and the like. Further, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

In addition, the display device includes a panel in which a display element is sealed, and a module in which an IC and the like including a controller are mounted on the panel. Regarding one mode of an element substrate before the display element is completed in a process for manufacturing the display device, the element substrate is provided with, in each of a plurality of pixels, a means (a wiring, a switch, or the like) which is configured to supply current to the display element. Specifically, the element substrate may be in a state in which only a pixel electrode of the display element is provided, a state after formation of a conductive film to be a pixel electrode and before etching of the conductive film to form the pixel electrode, or any other states.

A display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, the display device includes any of the following modules in its category: a module including a connector such as an flexible printed circuit (FPC), a tape automated bonding (TAB) tape, or a tape carrier package (TCP); a module having a TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip-on-glass (COG) method.

The appearance and a cross section of a liquid crystal display panel which is one mode of a semiconductor device will be described in this embodiment with reference to FIGS. 22A1 and 22A2, and FIG. 22B. FIGS. 22A1 and 22A2 are plan views of a panel in each of which highly reliable thin film transistors 4010 and 4011 that include oxide semiconductor layers of the In—Ga—Zn—O-based non-single-crystal films described in any of Embodiments 1 to 3 and a liquid crystal element 4013, which are formed over a first substrate 4001, are sealed with a sealant 4005 between the first substrate 4001 and a second substrate 4006. FIG. 22B corresponds to a cross-sectional view of FIGS. 22A1 and 22A2 taken along line M-N.

The sealant 4005 is provided so as to surround a pixel portion 4002 and a scan-line driver circuit 4004 which are provided over the first substrate 4001. The second substrate 4006 is provided over the pixel portion 4002 and the scan-line driver circuit 4004. Thus, the pixel portion 4002 and the scan-line driver circuit 4004 as well as a liquid crystal layer 4008 are sealed with the sealant 4005 between the first substrate 4001 and the second substrate 4006. A signal-line driver circuit 4003 which is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate which is prepared separately is mounted in a region that is different from the region surrounded by the sealant 4005 over the first substrate 4001.

Note that there is no particular limitation on a connection method of the driver circuit which is separately formed, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIG. 22A1 illustrates an example in which the signal-line driver circuit 4003 is mounted by a COG method, and FIG. 22A2 illustrates an example in which the signal-line driver circuit 4003 is mounted by a TAB method.

Each of the pixel portion 4002 and the scan-line driver circuit 4004 which are provided over the first substrate 4001 includes a plurality of thin film transistors. FIG. 22B illustrates the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scan-line driver circuit 4004. Insulating layers 4020 and 4021 are provided over the thin film transistors 4010 and 4011.

As each of the thin film transistors 4010 and 4011, the highly reliable thin film transistor described in any of Embodiments 1 to 3 including the In—Ga—Zn—O-based non-single-crystal film as the oxide semiconductor layer can be used. In this embodiment, the thin film transistors 4010 and 4011 are each an n-channel thin film transistor.

A pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. A counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. A portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap with each other corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with an insulating layer 4032 and an insulating layer 4033 which function as orientation films, respectively, and the liquid crystal layer 4008 is interposed between the insulating layers 4032 and 4033.

Note that the first substrate 4001 and the second substrate 4006 can be formed from glass, metal (typically, stainless steel), ceramic, or plastic. As plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. Alternatively, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

Reference numeral 4035 denotes a columnar spacer which is obtained by selectively etching of an insulating film and is provided to control a distance (a cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Alternatively, a spherical spacer may be used. In addition, the counter electrode layer 4031 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line are electrically connected to each other through conductive particles which are arranged between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealant 4005.

Alternatively, a blue phase liquid crystal without an orientation film may be used. A blue phase is a type of liquid crystal phase which appears just before a cholesteric liquid crystal changes into an isotropic phase when the temperature of the cholesteric liquid crystal is increased. A blue phase appears only within narrow temperature range; therefore, the liquid crystal layer 4008 is formed using a liquid crystal composition in which a chiral agent of 5 weight % or more is mixed in order to expand the temperature range. The liquid crystal composition including a blue phase liquid crystal and a chiral agent has a short response time of 10 μs to 100 μs and is optically isotropic; therefore, orientation treatment is not necessary and viewing angle dependence is small.

Note that in this embodiment, an example of a transmissive liquid crystal display device is described; however, an embodiment of the present invention can be applied to a reflective liquid crystal display device or a semi-transmissive liquid crystal display device.

Although a liquid crystal display device of this embodiment has a polarizer provided outer than the substrate (the viewer side) and a coloring layer and an electrode layer used for a display element provided inner than the substrate, which are arranged in that order, the polarizer may be inner than the substrate. The stacked structure of the polarizer and the coloring layer is not limited to that shown in this embodiment and may be set as appropriate in accordance with the materials of the polarizer and the coloring layer and the condition of the manufacturing process. Further, a light-blocking film which functions as a black matrix may be provided.

In this embodiment, in order to reduce the unevenness of the surface of the thin film transistors and to improve the reliability of the thin film transistors, the thin film transistors which are obtained in any of Embodiments 1 to 3 are covered with protective films or insulating layers (the insulating layers 4020 and 4021) which function as planarizing insulating films. Note that the protective film is provided to prevent entry of a contaminant impurity such as an organic substance, a metal substance, or moisture floating in the atmosphere, and therefore a dense film is preferable. The protective film may be formed using a single layer or a stack of layers of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film. Although the protective film is formed by a sputtering method in this embodiment, the method is not particularly limited and may be selected from a variety of methods.

Here, the insulating layer 4020 is formed to have a stacked structure as the protective film. Here, a silicon oxide film is formed by a sputtering method as a first layer of the insulating layer 4020. The use of a silicon oxide film for the protective film provides an advantageous effect of preventing hillock of an aluminum film used for the source and drain electrode layers.

Moreover, an insulating layer is formed as a second layer of the protective film. Here, a silicon nitride film is formed by a sputtering method as a second layer of the insulating layer 4020. When a silicon nitride film is used as the protective film, it is possible to prevent movable ions such as sodium from entering a semiconductor region to vary the electric characteristics of the TFT.

Further, after the protective film is formed, the oxide semiconductor layer may be annealed (at 300° C. to 400° C.).

Further, the insulating layer 4021 is formed as the planarizing insulating film. The insulating layer 4021 can be formed from an organic material having heat resistance, such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. As an alternative to such organic materials, it is possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the insulating layer 4021 may be formed by stacking a plurality of insulating films formed of these materials.

Note that a siloxane-based resin is a resin formed from a siloxane-based material as a starting material and having the bond of Si—O—Si. The siloxane-based resin may include as a substituent an organic group (for example, an alkyl group or an aryl group) or a fluoro group. Alternatively, the organic group may include a fluoro group.

The method for the formation of the insulating layer 4021 is not particularly limited and any of the following methods can be used depending on the material of the insulating layer 4021: a sputtering method; an SOG method; spin coating; dip coating; spray coating; a droplet discharge method (e.g., an inkjet method, screen printing, or offset printing); a doctor knife; a roll coater; a curtain coater; a knife coater; or the like. In the case of forming the insulating layer 4021 with the use of a material solution, annealing (300° C. to 400° C.) may be performed on the oxide semiconductor layer at the same time as a baking step. When the baking of the insulating layer 4021 and the annealing of the oxide semiconductor layer are performed at the same time, a semiconductor device can be manufactured efficiently.

The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed from a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

A conductive composition including a conductive macromolecule (also referred to as a conductive polymer) can be used for the pixel electrode layer 4030 and the counter electrode layer 4031. The pixel electrode formed using the conductive composition has preferably a sheet resistance of 10000 ohm/square or less and a transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive high molecule included in the conductive composition is preferably 0.1Ω·cm or less.

As the conductive macromolecule, a so-called π-electron conjugated conductive macromolecule can be used. As examples thereof, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds of them, and the like can be given.

Further, a variety of signals and potentials are supplied from an FPC 4018 to the signal-line driver circuit 4003 which is formed separately, the scan-line driver circuit 4004, and the pixel portion 4002.

In this embodiment, a connection terminal electrode 4015 is formed using the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013. A terminal electrode 4016 is formed using the same conductive film as the source and drain electrode layers included in the thin film transistors 4010 and 4011.

The connection terminal electrode 4015 is electrically connected to a terminal of the FPC 4018 through an anisotropic conductive film 4019.

Although FIGS. 22A1, 22A2, and 22B illustrate an example in which the signal-line driver circuit 4003 is formed separately and mounted on the first substrate 4001, this embodiment is not limited to this structure. The scan-line driver circuit may be separately formed and then mounted, or only part of the signal-line driver circuit or part of the scan-line driver circuit may be separately formed and then mounted.

FIG. 23 illustrates an example in which a liquid crystal display module is formed as a semiconductor device with the use of a TFT substrate 2600 which is manufactured by application of the TFT described in any of Embodiments 1 to 3.

FIG. 23 illustrates an example of a liquid crystal display module, in which the TFT substrate 2600 and a counter substrate 2601 are fixed to each other with a sealant 2602, and a pixel portion 2603 including a TFT and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided between the substrates to form a display region. The coloring layer 2605 is necessary to perform color display. In the case of the RGB system, respective colored layers corresponding to colors of red, green, and blue are provided for respective pixels. Polarizing plates 2606 and 2607 and a diffuser plate 2613 are provided outside the TFT substrate 2600 and the counter substrate 2601. A light source includes a cold cathode tube 2610 and a reflective plate 2611. A circuit board 2612 is connected to a wiring circuit portion 2608 of the TFT substrate 2600 through a flexible wiring board 2609 and includes an external circuit such as a control circuit and a power source circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate interposed therebetween.

For the liquid crystal display module, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, or the like can be used.

Through the aforementioned steps, a highly reliable liquid crystal display panel as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments, as appropriate.

Embodiment 6

In this embodiment, an example of electronic paper is shown as a semiconductor device to which the thin film transistor described in any of Embodiments 1 to 3 is applied.

FIG. 13 illustrates active matrix electronic paper as an example of a semiconductor device. As a thin film transistor 581 used for a semiconductor device, the thin film transistor described in any of Embodiments 1 to 3 can be applied.

The electronic paper in FIG. 13 is an example of a display device in which a twisting ball display system is employed. The twisting ball display system refers to a method in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed.

The thin film transistor 581 sealed between a substrate 580 and a substrate 596 has a bottom-gate structure in which the source or drain electrode layer is electrically connected to a first electrode layer 587 through an opening formed in an insulating layer 583, an insulating layer 584, and an insulating layer 585. Between the first electrode layer 587 and a second electrode layer 588, spherical particles 589 are provided. Each spherical particle 589 includes a black region 590 a and a white region 590 b, and a cavity 594 filled with liquid around the black region 590 a and the white region 590 b. The circumference of the spherical particle 589 is filled with filler 595 such as a resin (see FIG. 13). In this embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided over the same substrate 580 as the thin film transistor 581. The second electrode layer 588 and the common potential line are electrically connected through conductive particles arranged between a pair of substrates using the common connection portion described in any one of Embodiments 1 to 3.

Further, instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of approximately 10 μm to 200 μm, which is filled with transparent liquid, positively-charged white microparticles, and negatively-charged black microparticles, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and the black microparticles move to opposite sides to each other, so that white or black can be displayed. A display element using this principle is an electrophoretic display element, and is called electronic paper in general. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus an assistant light is unnecessary. Moreover, power consumption is low and a display portion can be recognized even in a dusky place. Furthermore, an image which is displayed once can be retained even when power is not supplied to the display portion. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which is also simply referred to as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.

Through the aforementioned steps, highly reliable electronic paper as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments, as appropriate.

Embodiment 7

In this embodiment, an example of a light-emitting display device will be shown as the semiconductor device to which the thin film transistor described in any of Embodiments 1 to 3 is applied. As an example of a display element of the display device, here, a light-emitting element utilizing electroluminescence is used. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is called an organic EL element and the latter is called an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and thus current flows. Then, those carriers (electrons and holes) are recombined, and thus the light-emitting organic compound is excited. When the light-emitting organic compound returns to a ground state from the excited state, light is emitted. Owing to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

Inorganic EL elements are classified according to their element structures into a dispersion type inorganic EL element and a thin-film type inorganic EL element. A dispersion type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film type inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

FIG. 20 illustrates an example of a pixel structure to which digital time grayscale driving can be applied, as an example of a semiconductor device to which one mode of the present invention is applied.

A structure and operation of a pixel to which digital time grayscale driving can be applied are described. In this example, one pixel includes two of the n-channel transistors described in any of Embodiments 1 to 3, in each of which a channel formation region includes an oxide semiconductor layer (In—Ga—Zn—O-based non-single-crystal film).

A pixel 6400 includes a switching transistor 6401, a driver transistor 6402, a light-emitting element 6404, and a capacitor 6403. A gate of the switching transistor 6401 is connected to a scan line 6406, a first electrode (one of a source electrode and a drain electrode) of the switching transistor 6401 is connected to a signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor 6401 is connected to a gate of the driver transistor 6402. The gate of the driver transistor 6402 is connected to a power supply line 6407 through the capacitor 6403, a first electrode of the driver transistor 6402 is connected to the power supply line 6407, and a second electrode of the driver transistor 6402 is connected to a first electrode (a pixel electrode) of the light-emitting element 6404. A second electrode of the light-emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed over one substrate, and the structure illustrated in FIG. 1A, FIG. 2A, or FIG. 3A may be employed using the connection portion as a common connection portion.

The second electrode (common electrode 6408) of the light-emitting element 6404 is set to a low power supply potential. The low power supply potential is a potential satisfying the low power supply potential <a high power supply potential when the high power supply potential set to the power supply line 6407 is a reference. As the low power supply potential, for example, GND, 0 V, or the like may be employed. A potential difference between the high power supply potential and the low power supply potential is applied to the light-emitting element 6404 and current is supplied to the light-emitting element 6404, so that the light-emitting element 6404 emits light. Here, in order to make the light-emitting element 6404 emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is greater than or equal to forward threshold voltage of the light-emitting element 6404.

Note that gate capacitor of the driver transistor 6402 may be used as a substitute for the capacitor 6403, so that the capacitor 6403 can be omitted. The gate capacitance of the driver transistor 6402 may be formed between the channel region and the gate electrode.

In the case of a voltage-input voltage driving method, a video signal is inputted to the gate of the driver transistor 6402 so that the driver transistor 6402 is in either of two states of being sufficiently turned on and turned off. That is, the driver transistor 6402 is made to operate in a linear region. In order to make the driver transistor 6402 operate in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driver transistor 6402. Note that a voltage higher than or equal to a total voltage of voltage of the power supply line and V_(th) of the driver transistor 6402 is applied to the signal line 6405.

In the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel structure as in FIG. 20 can be used by changing signal input.

In the case of performing analog grayscale driving, a voltage higher than or equal to forward voltage of the light-emitting element 6404+V_(th) of the driver transistor 6402 is applied to the gate of the driver transistor 6402. The forward voltage of the light-emitting element 6404 indicates a voltage at which a desired luminance is obtained, and includes at least forward threshold voltage. The video signal by which the driver transistor 6402 operates in a saturation region is inputted, so that current can be supplied to the light-emitting element 6404. In order make the driver transistor 6402 operate in a saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driver transistor 6402. When an analog video signal is used, it is possible to supply current to the light-emitting element 6404 in accordance with the video signal and perform analog grayscale driving.

Note that the pixel structure illustrated in FIG. 20 is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added to the pixel illustrated in FIG. 20.

Next, structures of a light-emitting element are described with reference to FIGS. 21A to 21C. A cross-sectional structure of a pixel is described here with an n-channel driver TFT taken as an example. TFTs 7001, 7011, and 7021 serving as driver TFTs used for a semiconductor device, which are illustrated in FIGS. 21A, 21B, and 21C, can be manufactured in a manner similar to that of the thin film transistor described in any of Embodiments 1 to 3. The TFTs 7001, 7011, and 7021 are highly reliable thin film transistors each including an In—Ga—Zn—O-based non-single-crystal film as an oxide semiconductor layer.

In order to extract light emitted from the light-emitting element, at least one of an anode and a cathode may be transparent. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top-emission structure in which light emission is extracted through the surface opposite to the substrate; a bottom-emission structure in which light emission is extracted through the surface on the substrate side; or a dual-emission structure in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel structure according to one embodiment of the present invention can be applied to a light-emitting element having any of these emission structures.

A light-emitting element having a top-emission structure is described with reference to FIG. 21A.

FIG. 21A is a cross-sectional view of a pixel in the case where the TFT 7001 serving as a driver TFT is an n-channel TFT and light generated in a light-emitting element 7002 is emitted to pass through an anode 7005. In FIG. 21A, a cathode 7003 of the light-emitting element 7002 is electrically connected to the TFT 7001 serving as a driver TFT, and a light-emitting layer 7004 and the anode 7005 are stacked in this order over the cathode 7003. The cathode 7003 can be formed using any of a variety of conductive materials as long as it has a low work function and reflects light. For example, Ca, Al, CaF, MgAg, AlLi, or the like is preferably used. The light-emitting layer 7004 may be formed using a single layer or by stacking a plurality of layers. When the light-emitting layer 7004 is formed by stacking a plurality of layers, the light-emitting layer 7004 is formed by stacking an electron-injecting layer, an electron-transporting layer, a light-emitting layer, a hole-transporting layer, and a hole-injecting layer in this order over the cathode 7003. It is not necessary to form all of these layers. The anode 7005 is formed using a light-transmitting conductive material, for example, a light-transmitting conductive film such as a film of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added may be used.

The light-emitting element 7002 corresponds to a region where the cathode 7003 and the anode 7005 sandwich the light-emitting layer 7004. In the case of the pixel illustrated in FIG. 21A, light is emitted from the light-emitting element 7002 to the anode 7005 side as indicated by an arrow.

Next, a light-emitting element having a bottom-emission structure is described with reference to FIG. 21B. FIG. 21B is a cross-sectional view of a pixel in the case where the driver TFT 7011 is an n-channel TFT, and light generated in a light-emitting element 7012 is emitted to a cathode 7013 side. In FIG. 21B, the cathode 7013 of the light-emitting element 7012 is formed over a light-transmitting conductive film 7017 which is electrically connected to the driver TFT 7011, and a light-emitting layer 7014 and an anode 7015 are stacked in this order over the cathode 7013. When the anode 7015 has a light-transmitting property, a light-blocking film 7016 which is provided to reflect or block light may be formed so as to cover the anode 7015. As in the case of FIG. 21A, the cathode 7013 can be formed using any of a variety of conductive materials as long as it has a low work function. Note that the cathode 7013 is formed to have a thickness that can transmit light (preferably, approximately 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm can be used as the cathode 7013. As in the case of FIG. 21A, the light-emitting layer 7014 may be formed using a single layer or by stacking a plurality of layers. As in the case of FIG. 21A, the anode 7015 is not required to transmit light, but can be formed using a light-transmitting conductive material. For the light-blocking film 7016, for example, metal or the like that reflects light can be used; however, the light-blocking film 7016 is not limited to a metal film. For example, a resin or the like to which black pigment is added can be used.

The light-emitting element 7012 corresponds to a region where the cathode 7013 and the anode 7015 sandwich the light-emitting layer 7014. In the case of the pixel illustrated in FIG. 21B, light is emitted from the light-emitting element 7012 to the cathode 7013 side as indicated by an arrow.

Next, a light-emitting element having a dual-emission structure is described with reference to FIG. 21C. In FIG. 21C, a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive film 7027 which is electrically connected to a driver TFT 7021, and a light-emitting layer 7024 and an anode 7025 are stacked in this order over the cathode 7023. As in the case of FIG. 21A, the cathode 7023 can be formed using any of a variety of conductive materials as long as it has a low work function. Note that the cathode 7023 is formed to have a thickness that can transmit light. For example, an Al film with a thickness of 20 nm can be used as the cathode 7023. As in the case of FIG. 21A, the light-emitting layer 7024 may be formed using a single layer or by stacking a plurality of layers. As in the case of FIG. 21A, the anode 7025 can be formed using a light-transmitting conductive material.

The light-emitting element 7022 corresponds to a region where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap with each other. In the pixel illustrated in FIG. 21C, light is emitted from the light-emitting element 7022 to both the anode 7025 side and the cathode 7023 side as indicated by arrows.

Although an organic EL element is described here as a light-emitting element, an inorganic EL element can be alternatively provided as a light-emitting element.

Note that in this embodiment, the example is shown in which a thin film transistor (a driver TFT) which controls the driving of a light-emitting element is electrically connected to the light-emitting element; however, a structure may be employed in which a current control TFT is connected between the driver TFT and the light-emitting element.

The semiconductor device described in this embodiment is not limited to the structures illustrated in FIGS. 21A to 21C, and can be modified in various ways based on the spirit of techniques of the present invention.

Next, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) which corresponds to one embodiment of the semiconductor device to which the thin film transistor described in any of Embodiments 1 to 3 is applied is described with reference to FIGS. 24A and 24B. FIG. 24A is a plan view of a panel in which a thin film transistor and a light-emitting element formed over a first substrate are sealed between the first substrate and a second substrate with a sealant, and FIG. 24B is a cross-sectional view taken along H-I of FIG. 24A.

A sealant 4505 is provided so as to surround a pixel portion 4502, signal-line driver circuits 4503 a and 4503 b, and scan-line driver circuits 4504 a and 4504 b, which are provided over a first substrate 4501. In addition, a second substrate 4506 is provided over the pixel portion 4502, the signal-line driver circuits 4503 a and 4503 b, and the scan-line driver circuits 4504 a and 4504 b. Accordingly, the pixel portion 4502, the signal-line driver circuits 4503 a and 4503 b, and the scan-line driver circuits 4504 a and 4504 b are sealed together with filler 4507 by the first substrate 4501, the sealant 4505, and the second substrate 4506. In this manner, it is preferable that the pixel portion 4502, the signal-line driver circuits 4503 a and 4503 b, and the scan-line driver circuits 4504 a and 4504 b be packaged (sealed) with a protective film (such as an attachment film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the pixel portion 4502, the signal-line driver circuits 4503 a and 4503 b, and the scan-line driver circuits 4504 a and 4504 b are not exposed to external air.

The pixel portion 4502, the signal-line driver circuits 4503 a and 4503 b, and the scan-line driver circuits 4504 a and 4504 b provided over the first substrate 4501 each include a plurality of thin film transistors, and a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 4509 included in the signal-line driver circuit 4503 a are illustrated as an example in FIG. 24B.

As the thin film transistors 4509 and 4510, highly reliable thin film transistors described in any of Embodiments 1 to 3 including the In—Ga—Zn—O-based non-single-crystal films as oxide semiconductor layers can be employed. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

Moreover, reference numeral 4511 denotes a light-emitting element. A first electrode layer 4517 which is a pixel electrode included in the light-emitting element 4511 is electrically connected to source and drain electrode layers of the thin film transistor 4510. Note that although the light-emitting element 4511 has a stacked structure of the first electrode layer 4517, an electroluminescent layer 4512, and a second electrode layer 4513, the structure of the light-emitting element 4511 is not limited to the structure described in this embodiment. The structure of the light-emitting element 4511 can be changed as appropriate depending on a direction in which light is extracted from the light-emitting element 4511, for example.

A partition 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition 4520 be formed using a photosensitive material to have an opening on the first electrode layer 4517 so that a sidewall of the opening is formed as a tilted surface with continuous curvature.

The electroluminescent layer 4512 may be formed using a single layer or by stacking a plurality of layers.

In order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting element 4511, a protective film may be formed over the second electrode layer 4513 and the partition 4520. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, a variety of signals and potentials are supplied from FPCs 4518 a and 4518 b to the signal-line driver circuits 4503 a and 4503 b, the scan-line driver circuits 4504 a and 4504 b, or the pixel portion 4502.

In this embodiment, a connection terminal electrode 4515 is formed using the same conductive film as the first electrode layer 4517 included in the light-emitting element 4511. A terminal electrode 4516 is formed using the same conductive film as the source and drain electrode layers included in the thin film transistors 4509 and 4510.

The connection terminal electrode 4515 is electrically connected to a terminal included in the FPC 4518 a through an anisotropic conductive film 4519.

The second substrate 4506 located in the direction in which light is extracted from the light-emitting element 4511 needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

As the filler 4507, an ultraviolet curable resin or a thermosetting resin as well as inert gas such as nitrogen or argon can be used. For example, polyvinyl chloride (PVC), acrylic, polyimide, an epoxy resin, a silicone resin, polyvinyl butyral (PVB), or ethylene vinyl acetate (EVA) can be used. In this embodiment, nitrogen is used for the filler 4507.

In addition, if needed, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retarder plate (a quarter-wave plate, a half-wave plate), or a color filter may be provided on an emission surface of the light-emitting element, as appropriate. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment can be performed by which reflected light is diffused in the depression/projection of the surface and glare can be reduced.

As the signal-line driver circuits 4503 a and 4503 b and the scan-line driver circuits 4504 a and 4504 b, driver circuits formed using a single crystal semiconductor film or polycrystalline semiconductor film over a substrate separately prepared may be mounted. In addition, only the signal-line driver circuit or only part thereof, or only the scan-line driver circuit or only part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated in FIGS. 24A and 24B.

Through the aforementioned steps, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments, as appropriate.

Embodiment 8

A semiconductor device to which the thin film transistor described in any of Embodiments 1 to 3 is applied can be applied as electronic paper. Electronic paper can be used for electronic devices of every field for displaying information. For example, electronic paper can be used for electronic book (e-book), posters, advertisements in vehicles such as trains, display in a variety of cards such as credit cards, and so on. Examples of such electronic devices are illustrated in FIGS. 25A and 25B and FIG. 26.

FIG. 25A illustrates a poster 2631 formed using electronic paper. If the advertizing medium is printed paper, the advertisement is replaced by manpower; however, when electronic paper is used, the advertisement display can be changed in a short time. Moreover, a stable image can be obtained without display deterioration. Note that the poster may send and receive information wirelessly.

FIG. 25B illustrates an advertisement 2632 in a vehicle such as a train. If the advertizing medium is printed paper, the advertisement is replaced by manpower; however, when electronic paper is used, the advertisement display can be changed in a short time without much manpower. Moreover, a stable image can be obtained without display deterioration. Note that the advertisement in a vehicle may send and receive information wirelessly.

FIG. 26 illustrates an example of an electronic book 2700. For example, the electronic book 2700 includes two chassis of a chassis 2701 and a chassis 2703. The chassis 2701 and 2703 are bound with each other by an axis portion 2711, along which the electronic book 2700 can be opened and closed. With such a structure, operation as a paper book is achieved.

A display portion 2705 is incorporated in the chassis 2701, and a display portion 2707 is incorporated in the chassis 2703. The display portions 2705 and 2707 may display a series of images, or may display different images. With the structure where different images are displayed in different display portions, for example, a display portion on the right side (the display portion 2705 in FIG. 26) can display text, and a display portion on the left side (the display portion 2707 in FIG. 26) can display images.

FIG. 26 illustrates an example in which the chassis 2701 is provided with an operation portion and the like. For example, the chassis 2701 is provided with a power supply 2721, an operation key 2723, a speaker 2725, and the like. The page can be turned with the operation key 2723. Note that a keyboard, a pointing device, and the like may be provided on the same plane as the display portion of the chassis. Further, a rear surface or a side surface of the chassis may be provided with an external connection terminal (an earphone terminal, a USB terminal, a terminal which can be connected with a variety of cables such as an AC adapter or a USB cable, and the like), a storage medium inserting portion, or the like. Moreover, the electronic book 2700 may also have a function of an electronic dictionary.

Further, the electronic book 2700 may send and receive information wirelessly. Desired book data or the like can be purchased and downloaded from an electronic book server wirelessly.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments, as appropriate.

Embodiment 9

The semiconductor device including the thin film transistor described in any of Embodiments 1 to 3 can be applied to a variety of electronic devices (including game machines). As the electronic devices, for example, there are a television device (also referred to as TV or a television receiver), a monitor for a computer or the like, a digital camera, a digital video camera, a digital photo frame, a cellular phone (also referred to as a mobile phone or a portable telephone device), a portable game machine, a portable information terminal, an audio playback device, a large game machine such as a pachinko machine, and the like.

FIG. 27A illustrates an example of a television device 9600. A display portion 9603 is incorporated in a chassis 9601 of the television device 9600. The display portion 9603 can display images. Here, the chassis 9601 is supported on a stand 9605.

The television device 9600 can operate by an operation switch of the chassis 9601 or a separate remote controller 9610. The channel and volume can be controlled with operation keys 9609 of the remote controller 9610, and the images displayed in the display portion 9603 can be controlled. Moreover, the remote controller 9610 may have a display portion 9607 in which the information outgoing from the remote controller 9610 is displayed.

Note that the television device 9600 is provided with a receiver, a modem, and the like. With the use of the receiver, general television broadcasting can be received. Moreover, when the display device is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver, between receivers, or the like) information communication can be performed.

FIG. 27B illustrates an example of a digital photo frame 9700. For example, a display portion 9703 is incorporated in a chassis 9701 of the digital photo frame 9700. The display portion 9703 can display a variety of images. For example, image data taken by a digital camera or the like is displayed, so that the digital photo frame can function in a manner similar to that of a general picture frame.

Note that the digital photo frame 9700 is provided with an operation portion, an external connection terminal (such as a USB terminal, a terminal which can be connected to a variety of cables including a USB cable, or the like), a storage medium inserting portion, and the like. These structures may be incorporated on the same plane as the display portion; however, they are preferably provided on the side surface or rear surface of the display portion because the design is improved. For example, a memory including image data taken by a digital camera is inserted into the storage medium inserting portion of the digital photo frame and the image data is imported. Then, the imported image data can be displayed in the display portion 9703.

The digital photo frame 9700 may send and receive information wirelessly. In this case, desired image data can be wirelessly imported into the digital photo frame 9700 and can be displayed therein.

FIG. 28A illustrates a portable game machine including a chassis 9881 and a chassis 9891 which are jointed with a connector 9893 so as to be able to open and close. A display portion 9882 is incorporated in the chassis 9881, and a display portion 9883 is incorporated in the chassis 9891. The portable game machine illustrated in FIG. 28A additionally includes a speaker portion 9884, a storage medium inserting portion 9886, an LED lamp 9890, an input means (operation keys 9885, a connection terminal 9887, a sensor 9888 (including a function of measuring force, displacement, position, speed, acceleration, angular speed, the number of rotations, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, tilt angle, vibration, smell, or infrared ray), and a microphone 9889), and the like. Needless to say, the structure of the portable game machine is not limited to the above, and may be any structure as long as at least a semiconductor device according to one embodiment of the present invention is provided. Moreover, another accessory may be provided as appropriate. The portable game machine illustrated in FIG. 28A has a function of reading out a program or data stored in a storage medium to display it on the display portion and a function of sharing information with another portable game machine by wireless communication. The functions of the portable game machine illustrated in FIG. 28A are not limited to these, and the portable game machine can have a variety of functions.

FIG. 28B illustrates an example of a slot machine 9900 which is a large game machine. A display portion 9903 is incorporated in a chassis 9901 of the slot machine 9900. The slot machine 9900 additionally includes an operation means such as a start lever or a stop switch, a coin slot, a speaker, and the like. Needless to say, the structure of the slot machine 9900 is not limited to the above, and may be any structure as long as at least a semiconductor device according to one embodiment of the present invention is provided. Moreover, another accessory may be provided as appropriate.

FIG. 29A illustrates an example of a cellular phone 1000. The cellular phone 1000 includes a chassis 1001 in which a display portion 1002 is incorporated, and moreover includes an operation button 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

Information can be inputted to the cellular phone 1000 illustrated in FIG. 29A by touching the display portion 1002 with a finger or the like. Moreover, operations such as making a phone call or texting message can be performed by touching the display portion 1002 with a finger or the like.

There are mainly three screen modes of the display portion 1002. The first mode is a display mode mainly for displaying an image. The second mode is an input mode mainly for inputting information such as text. The third mode is a display-and-input mode in which two modes of the display mode and the input mode are mixed.

For example, in the case of making a phone call or texting message, the display portion 1002 is set to a text input mode where text input is mainly performed, and text input operation can be performed on a screen. In this case, it is preferable to display a keyboard or number buttons on almost the entire screen of the display portion 1002.

When a detection device including a sensor that detects inclination, such as a gyroscope or an acceleration sensor, is provided inside the cellular phone 1000, display in the screen of the display portion 1002 can be automatically switched by judging the direction of the cellular phone 1000 (whether the cellular phone 1000 is placed horizontally or vertically for a landscape mode or a portrait mode).

Further, the screen modes are switched by touching the display portion 1002 or operating the operation button 1003 of the chassis 1001. Alternatively, the screen modes can be switched depending on kinds of image displayed in the display portion 1002. For example, when a signal for an image displayed in the display portion is data of moving images, the screen mode is switched to the display mode. When the signal is text data, the screen mode is switched to the input mode.

Moreover, in the input mode, when input by touching the display portion 1002 is not performed within a specified period while a signal detected by an optical sensor in the display portion 1002 is detected, the screen mode may be controlled so as to be switched from the input mode to the display mode.

The display portion 1002 can also function as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken by touching the display portion 1002 with the palm or the finger, whereby personal authentication can be performed. Moreover, when a backlight which emits near-infrared light or a sensing light source which emits near-infrared light is provided in the display portion, a finger vein, a palm vein, or the like can be taken.

FIG. 29B illustrates an example of a cellular phone as well. The cellular phone in FIG. 29B includes a display device 9410 having, in a chassis 9411, a display portion 9412 and operation buttons 9413, and a communication device 9400 having, in a chassis 9401, operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light-emitting portion 9406 which emits light when a phone call is received. The display device 9410 having a display function can be detached from or attached to the communication device 9400 having a phone function in the two directions indicated by arrows. Accordingly, the display device 9410 and the communication device 9400 can be attached to each other along respective short axes or long axes. Alternatively, in the case where only the display function is needed, the display device 9410 is detached from the communication device 9400, and then the display device 9410 can be used alone. Images or input information can be transmitted and received by wireless or wire communication between the communication device 9400 and the display device 9410, each of which includes a chargeable battery.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments, as appropriate.

The present application is based on Japanese Patent Application serial No. 2008-333581 filed with Japan Patent Office on Dec. 26, 2008, the entire contents of which are hereby incorporated by reference. 

1. A semiconductor device comprising: a gate electrode layer; a gate insulating layer over the gate electrode layer; a plurality of oxide clusters over the gate insulating layer; an oxide semiconductor layer over the gate insulating layer and the plurality of oxide clusters; and source and drain electrode layers over the oxide semiconductor layer, wherein the plurality of oxide clusters have electrical conductivity, wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other, and wherein the oxide semiconductor layer and the drain electrode layer are electrically connected to each other.
 2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes at least one of indium, gallium, and zinc.
 3. The semiconductor device according to claim 1, wherein the plurality of oxide clusters include at least one of indium, zinc, tin, molybdenum, and tungsten.
 4. The semiconductor device according to claim 1, wherein the plurality of oxide clusters include at least one of indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, molybdenum oxide, and tungsten oxide.
 5. The semiconductor device according to claim 1, wherein electrical conductance of the plurality of oxide clusters is higher than electrical conductance of the oxide semiconductor layer.
 6. The semiconductor device according to claim 1, wherein a film thickness of the oxide semiconductor layer is equal to or greater than 30 nm and equal to or less than 100 nm.
 7. The semiconductor device according to claim 1, wherein a height of the plurality of oxide clusters from a reference surface in contact with the gate insulating layer is equal to or greater than 3 nm and equal to or less than 5 nm.
 8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has a region which is between the source and drain electrode layers and whose thickness is smaller than a thickness of a region overlapping with the source and drain electrode layers.
 9. The semiconductor device according to claim 1, wherein a channel protective layer including an inorganic material is formed over the oxide semiconductor layer.
 10. A semiconductor device comprising: a gate electrode layer; a gate insulating layer over the gate electrode layer; a plurality of oxide clusters over the gate insulating layer; an oxide semiconductor layer over the gate insulating layer and the plurality of oxide clusters; a buffer layer having n-type electrical conductivity over the oxide semiconductor layer; and source and drain electrode layers over the buffer layer, wherein the plurality of oxide clusters have electrical conductivity, wherein a carrier concentration of the buffer layer is higher than a carrier concentration of the oxide semiconductor layer, wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other with the buffer layer interposed therebetween, and wherein the oxide semiconductor layer and the drain electrode layer are electrically connected to each other with the buffer layer interposed therebetween.
 11. The semiconductor device according to claim 10, wherein the oxide semiconductor layer and the buffer layer include at least one of indium, gallium, and zinc.
 12. The semiconductor device according to claim 10, wherein the plurality of oxide clusters include at least one of indium, zinc, tin, molybdenum, and tungsten.
 13. The semiconductor device according to claim 12, wherein the plurality of oxide clusters include at least one of indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, molybdenum oxide, and tungsten oxide.
 14. The semiconductor device according to claim 10, wherein electrical conductance of the plurality of oxide clusters is higher than electrical conductance of the oxide semiconductor layer.
 15. The semiconductor device according to claim 10, wherein a film thickness of the oxide semiconductor layer is equal to or greater than 30 nm and equal to or less than 100 nm.
 16. The semiconductor device according to claim 10, wherein a height of the plurality of oxide clusters from a reference surface in contact with the gate insulating layer is equal to or greater than 3 nm and equal to or less than 5 nm.
 17. The semiconductor device according to claim 10, wherein the oxide semiconductor layer has a region which is between the source and drain electrode layers and whose thickness is smaller than a thickness of a region overlapping with the source and drain electrode layers.
 18. The semiconductor device according to claim 10, wherein a channel protective layer including an inorganic material is formed over the oxide semiconductor layer.
 19. A method for manufacturing a semiconductor device comprising: forming a gate electrode layer over a substrate; forming a gate insulating layer over the gate electrode layer; forming a plurality of oxide clusters having electrical conductivity over the gate insulating layer in a dispersed manner; forming an oxide semiconductor film over the gate insulating layer and the plurality of oxide clusters by a sputtering method; forming an island-like second oxide semiconductor film with an etching method of the oxide semiconductor film; forming a conductive layer over the island-like second oxide semiconductor film; and forming an oxide semiconductor layer and source and drain electrode layers with an etching method of the island-like second oxide semiconductor film and the conductive layer.
 20. The method for manufacturing a semiconductor device according to claim 19, wherein the oxide semiconductor film includes at least one of indium, gallium, and zinc.
 21. The method for manufacturing a semiconductor device according to claim 19, wherein the plurality of oxide clusters includes at least one of indium, zinc, tin, molybdenum, and tungsten.
 22. The method for manufacturing a semiconductor device according to claim 19, wherein electrical conductance of the plurality of oxide clusters is made higher than electrical conductance of the oxide semiconductor layer.
 23. The method for manufacturing a semiconductor device according to claim 19, wherein the plurality of oxide clusters are formed by a sputtering method so as to have a height of equal to or greater than 3 nm and equal to or less than 5 nm from a reference surface in contact with the gate insulating layer.
 24. The method for manufacturing a semiconductor device according to claim 19, wherein the oxide semiconductor layer has a region which is between the source and drain electrode layers and whose thickness is smaller than a thickness of a region overlapping with the source and drain electrode layers.
 25. An electronic device having the semiconductor device according to claim
 1. 26. An electronic device having the semiconductor device according to claim
 10. 